DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3-9, 19-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The exact term “semiconductor module” has never been used in the Specification of the parent case and appears for the first time only in the instant Application’s claims 3-9, 19-20. Since no special meaning of “semiconductor module” is clear from the Specification, then any die/chip (since dies/chips are fabricated from semiconductors) in the applied reference(s) can be referred to as a “semiconductor module”. If Applicant agrees with the above interpretation, then no changes are necessary. Otherwise, the phrase will be considered as not being appropriately clear.
So, for the purposes of the rejection below any die/chip (since dies/chips are fabricated from semiconductors) in the applied reference(s) can be referred to as a “semiconductor module”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 20190146166; “Wang”).
Regarding claim 1, Wang teaches a package structure, comprising: a package substrate comprising a first die 130 including a photonic integrated circuit 130; a second die 190 on the first die/PIC 130 and including an electronic integrated circuit 190 electrically coupled to the photonic integrated circuit 130 (e.g., PIC/die 130; fig. 3F); and a third die 200 on the package substrate (e.g., fig. 3F) adjacent the second die 190.
Thus claim 1 is met.
Regarding claim 2, Wang teaches package structure of claim 1 (see above), wherein the second die 190 is communicatively coupled to the third die 200 through the first die/PIC 130 (e.g., all named elements are attached/communicatively coupled mechanically, photonically, and/or electronically either directly or indirectly; fig. 3F).
Thus claim 2 is met.
Regarding claim 3, Wang teaches package structure of claim 1 (see above), further comprising: a semiconductor module 200 including the third die 200 (e.g., fig. 3F), wherein at least a portion of the semiconductor module 200 is on the first die/PIC 130 and electrically coupled to the photonic integrated circuit 130 (e.g., fig. 3F; EIC 190 is electrically coupled to the PIC/die 130 and semiconductor module/die 200 at least requires electrical connection via EIC 190 thus providing at least an indirect electrical coupling between die/PIC 130 and semiconductor module/die 200).
Thus claim 3 is met.
Regarding claim 4, Wang teaches package structure of claim 3 (see above), wherein the package substrate further comprises: a redistribution layer (RDL) 142 (e.g., fig. 3F) structure including a metal interconnect structure, wherein the first die 130 is on the RDL structure 142 (e.g., fig. 3F); a molding material layer 160 on the RDL structure 142 and encapsulating the first die/PIC 130; and a via structure 144 (e.g., fig. 3F) in the molding material layer 160 and electrically coupling the semiconductor module 200 to the metal interconnect structure (e.g., the metal interconnect structure shows in layer 142 in fig. 3F).
Thus claim 4 is met.
Regarding claim 5, Wang teaches package structure of claim 4 (see above), wherein the package substrate further comprises: a core substrate 210; and a first package substrate molding material layer 214 encapsulating the core substrate 210 (e.g., fig. 3F), wherein the RDL structure 142is on the first package substrate molding material layer and electrically coupled to the core substrate 210 (e.g., fig. 3F).
Thus claim 5 is met.
Regarding claim 6, Wang teaches package structure of claim 4 (see above), wherein the first die 130 comprises an upper surface that is substantially coplanar with an upper surface of molding material layer (e.g., fig. 3F).
Thus claim 6 is met.
Regarding claim 14, Wang teaches a method of making a package structure, the method comprising: forming a package substrate including a first die 130 comprising a photonic integrated circuit 130 (e.g., fig. 3F); attaching a second die 190 to the first die 130 (e.g., fig. 3F), wherein the second die 190 includes an electronic integrated circuit electrically coupled to the photonic integrated circuit (e.g., fig. 3F); and attaching a third die 200 to the package substrate adjacent the second die 190 (e.g., fig. 3F).
Thus claim 14 is met.
Regarding claim 15, Wang teaches the method of claim 14 (see above), wherein the forming of the package substrate comprises: encapsulating the first die 130 in a molding material layer 160 including a via structure 144; and forming a redistribution layer (RDL) structure 142 including a metal interconnect structure on a bottom side of the molding material layer 160 (e.g., fig. 3F).
Regarding claim 16, Wang teaches the method of claim 15 (see above), wherein the encapsulating of the first die comprises encapsulating the first die such that an upper surface of the first die/PIC 130 is substantially coplanar with an upper surface of molding material layer 160 (e.g., fig. 3F).
Regarding claim 17, Wang teaches the method of claim 15 (see above), wherein the forming of the package substrate further comprises: attaching a core substrate 210 on a bottom side of the RDL structure 142; and encapsulating the core substrate 210 in a first package substrate molding material layer 214 (e.g., fig. 3F).
Regarding claim 18, Wang teaches the method of claim 14 (see above), wherein the attaching of the third die comprises attaching the third die 200 such that the second die 190 is communicatively coupled to the third die 200 through the first die 200 (e.g., all named elements are attached/communicatively coupled mechanically, photonically, and/or electronically either directly or indirectly; fig. 3F).
Regarding claim 19, Wang teaches the method of claim 14 (see above), the method of claim 14, wherein the attaching of the third die 200 comprises attaching a semiconductor module 200 including the third die 200 to the package substrate such that at least a portion of the semiconductor module 200 is on the first die 130 (e.g., fig. 3F) and electrically coupled to the photonic integrated circuit (e.g., fig. 3F; EIC 190 is electrically coupled to the PIC/die 130 and semiconductor module/die 200 at least requires electrical connection via EIC 190 thus providing at least an indirect electrical coupling between die/PIC 130 and semiconductor module/die 200).
Regarding claim 20, Wang teaches a semiconductor device comprising: a photonic/PIC die 130 embedded in a molding material layer 160 (e.g., fig. 3F); an electronic die 190 attached to the photonic die 130 and electrically coupled to the photonic die 130 (e.g., fig. 3F); and a module 200 including a semiconductor die 200 attached to the photonic die 130 and the molding material layer 160 (e.g., all named elements are attached/communicatively coupled mechanically, photonically, and/or electronically either directly or indirectly; fig. 3F).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20190146166; “Wang”).
Regarding claim 10, Wang teaches package structure of claim 1 (see above).
Wang does not explicitly state wherein the.
However, it was well-known for second die/EIC to comprise a controller configured to control an operation in the photonic integrated circuit. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for second die/EIC to comprise a controller configured to control an operation in the photonic integrated circuit at least for the purpose of properly controlling circuits on the PIC 130 chip/die.
Thus claim 10 is rejected.
Allowable Subject Matter
Claims 7-9, 11-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. For claims 7-9, this statement is contingent upon overcoming the 112 rejection(s) above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mr. Michael Mooney whose telephone number is 571-272-2422. The examiner can normally be reached during weekdays, M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached on 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center. Should you have questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). For checking the filing status of an application, please refer to <https://www.uspto.gov/patents/apply/checking-application-status/check-filing-status-your-patent-application>.
/MICHAEL P MOONEY/Primary Examiner, Art Unit 2874
Prosecution Insights