DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on February 25, 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 30, 2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Nitride Semiconductor Device With Warping Suppression and Manufacturing Method Thereof
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation “more deep energy levels including either or both of levels with energy depths from conduction band of not less than 0.6 eV and not more than 0.7 eV and not less than 1.5 eV and not more than 1.6 eV are formed than shallow donor levels.” It is unclear how an energy level can be both not less than 0.6 eV and not more than 0.7 eV AND not less than 1.5 eV and not more than 1.6 eV. For purposes of examination this will be interpreted as “more deep energy levels including either or both of levels with energy depths from conduction band of not less than 0.6 eV and not more than 0.7 eV or not less than 1.5 eV and not more than 1.6 eV are formed than shallow donor levels.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9-10, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yaegashi (US 2006/0220042) in view of Kinoshita (US 2022/0195622). Claim 1, Yaegashi discloses (Fig. 6C) a nitride semiconductor device comprising: an SiC substrate (10a, SiC substrate with a 1E19 carrier density , Para {0046]) having a first principal surface (top surface of 10a) and a second principal surface (bottom surface of 10a) opposite thereto; a low resistance SiC layer (12a, SiC buffer layer with a 2E19 carrier density, Para [0046]) that is formed on the first principal surface (12a is formed on top surface of 10a); a high resistance SiC layer (14a, SiC drift layer with a 2E16 carrier density, Para [0046]) that is formed on the low resistance SiC layer (14a is on 12a); a nitride epitaxial layer (25, GaN-based semiconductor layer, Para [0047]) that is disposed on the high resistance SiC layer (25 is disposed on 14a).
Yaegashi does not explicitly disclose the low resistance SiC is lower in resistivity than the SiC substrate; and the high resistance SiC layer is higher in resistivity than the low resistance SiC layer. However, Kinoshita discloses that higher carrier density in SiC results in lower resistivity (Para [0034]). Therefore it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention for 12a to have a lower resistance than 10a (since 12a has higher carrier density than 10a) and for 14a to have a higher resistance than 12a (since 12a has a higher carrier density than 14a). Claim 9, Yaegashi in view of Kinoshita discloses the nitride semiconductor device according to Claim 1. Yaegashi discloses (Fig. 6C) wherein a thickness of the high resistance SiC layer (14a) is not less than 5 µm (14a may have a thickness of 10 µm, Para [0046]). Claim 10, Yaegashi in view of Kinoshita discloses the nitride semiconductor device according to Claim 1. Yaegashi discloses (Fig. 6C) wherein a thickness of the nitride epitaxial layer (25) is not more than 2.5 µm (25 comprises layers 18/20/22 where 18 is 100 nm, 20 is 100 nm, and 22 is 100 nm resulting in a total of 300 nm).
Claim 19, Yaegashi discloses (Figs. 6A-6C) a method for manufacturing a nitride semiconductor device comprising: a step of forming, on a first principal surface (top surface of 10a) of an SiC substrate (10a, SiC substrate with a 1E19 carrier density , Para [0046]) having the first principal surface and a second principal surface (bottom surface of 10a) opposite thereto, a low resistance SiC layer (12a, SiC buffer layer with a 2E19 carrier density, Para [0046]) a step of forming, on the low resistance SiC layer (12a, SiC buffer layer with a 2E19 carrier density, Para [0046]), a high resistance SiC layer (14a, SiC drift layer with a 2E16 carrier density, Para [0046]) and a step of forming a nitride epitaxial layer (25, GaN-based semiconductor layer, Para [0047]) on the high resistance SiC layer (25 is on 14a). Yaegashi does not explicitly disclose forming the low resistance SiC layer that is lower in resistivity than the SiC substrate; and forming the high resistance SiC layer that is higher in resistivity than the low resistance SiC layer. However, Kinoshita discloses that higher carrier density in SiC results in lower resistivity (Para [0034]). Therefore it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention for 12a to have a lower resistance than 10a (since 12a has higher carrier density than 10a) and for 14a to have a higher resistance than 12a (since 12a has a higher carrier density than 14a).
Allowable Subject Matter
Claims 2-8 and 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Yaegashi (US 2006/0220042), Kinoshita (US 2022/0195622), Roberts (US 2019/0013196), Sriram (US 2004/0099888), D’Anna (US Pat. No. 6,521,923), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 2 (from which claims 3-7 depend), wherein the resistivity of the low resistance SiC layer is not more than 0.01 Ω∙cm and the resistivity of the high resistance SiC layer is not less than 10 Ω∙cm.
Regarding Claim 8, wherein a thickness of the low resistance SiC layer is not less than 2 μm.
Regarding Claim 12 (from which claims 13-14 depend), a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, constitutes an electron supply layer, and is higher in bandgap than the first nitride semiconductor layer.
Regarding Claim 15 (from which claim 17 depends), a contact hole reaching from a front surface of the nitride epitaxial layer to an intermediate thickness of the low resistance SiC layer is formed and the source electrode is electrically connected to the low resistance SiC layer via the contact hole.
Regarding Claim 16 (from which claim 18 depends), a contact hole reaching from a front surface of the nitride epitaxial layer to an intermediate thickness of the SiC substrate is formed, and the source electrode is electrically connected to the SiC substrate via the contact hole.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Roberts (US 2019/0013196) discloses the connection between carrier concentration and high parasitic resistivities (Para [0068]).
Sriram (US 2004/0099888) discloses (Fig. 5) a SiC substrate 10, a buffer layer 12, second buffer layer SiC 16 and n-type conductivity channel 18.
D’Anna (US Pat. No. 6,521,923) discloses (Fig. 7) discloses a heavily doped SiC substrate 126 with a resistivity smaller than .1 ohm-cm.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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