DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2023/0335469 A1 hereinafter referred to as “Wang”).
With respect to claim 1, Wang discloses, in Figs.1A-11, a semiconductor device comprising: a first lower/(upper) interlayer insulating layer (162); an insulating pattern (151) extending in a first horizontal direction on an upper/(lower) surface of the first lower interlayer insulating layer (162) (see Par.[0064]-[0067] wherein an etch stop layer 162 is formed over the S/D contact structure 156 and the mask layers 152, and a dielectric layer 164 is formed over the etch stop layer 162; see Par.[0106]-[0108] wherein the mask layer 151 is made of SiO.sub.2, Si.sub.3N.sub.4, SiON, SiOCN, SiOCH, or the like); a first plurality of nanosheets (108’) stacked apart from one another in a vertical direction on the insulating pattern (151); a second plurality of nanosheets (108’) stacked apart from one another in the vertical direction on the insulating pattern (151), the second plurality of nanosheets (108) spaced apart from the first plurality of nanosheets (108’) in the first horizontal direction (see Par.[0038], [0041]-[0042], [0049], [0051]-[0053] wherein the nanostructures 108′ are formed, the gate structures 142 are formed wrapped around the nanostructures 108′; the gate structures 142 wrap around the nanostructures 108′ to form gate-all-around transistor structures in accordance with some embodiments); a first gate electrode (148) extending in a second horizontal direction different from the first horizontal direction on the insulating pattern (151), the first gate electrode (148) surrounding the first plurality of nanosheets (108’) (see Par.[0051] wherein the gate structure 142 includes an interfacial layer 144, a gate dielectric layer 146, and a gate electrode layer 148); a second gate electrode (148) extending in the second horizontal direction on the insulating pattern (151), the second gate electrode (148) surrounding the second plurality of nanosheets (108’), the second gate electrode (148) spaced apart from the first gate electrode (148) in the first horizontal direction; a source/drain region (136) between the first and second gate electrodes (148) on the insulating pattern (151); a source/drain contact (156, 160, 158, 184, 188) penetrating the first lower interlayer insulating layer (162) and the insulating pattern (151) in the vertical direction, the source/drain contact (156, 160, 158, 188) electrically connected to the source/drain region (136) (see Par.[0056]-[0057] wherein S/D contact structures 156 are formed over the S/D structures 136; the contact openings may be formed through the contact etch stop layer 138, the interlayer dielectric layer 140, the etch stop layer 150 and the dielectric layer 152 to expose the top surfaces of the S/D structures 136, and the silicide layers 154 and the S/D contact structure 156 may be formed in the contact openings; see Par.[0059] wherein the liners 158, the barrier layers 160, and the S/D contact structure 156 are formed over the silicide layers 154 in the contact openings and a polishing process is performed); and a gate contact (148, 146, 169, 168, 186, 188) penetrating the first lower interlayer insulating layer (151) and the insulating pattern (162) in the vertical direction, the gate contact (148, 146, 169, 168, 186) electrically connected to the second gate electrode (148), at least a portion (188) of a sidewall of the gate contact (148, 146, 169, 168, 186, 188) contacting the source/drain contact (156, 160, 158, 184, 188), wherein the source/drain contact (156, 160, 158, 184, 188) and the gate contact are integrally formed (148, 146, 169, 168, 186, 188) (see Par.[0051], [0053]-[0054] wherein the gate dielectric layers 146 are made of one or more layers of dielectric materials, such as HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO.sub.1—Al2O.sub.3) alloy, another suitable high-k dielectric material, or a combination thereof; the gate electrode layers 148 are formed on the gate dielectric layer 146. In some embodiments, the gate electrode layers 148 are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof; see Par.[0069]-[0072] wherein the conductive layer 169 is tungsten (W), ruthenium (Ru), molybdenum (Mo), or the like. In some embodiments, the conductive layer 169 is formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes; the barrier layer 168 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another applicable material; see Par.[0086]-[0087] wherein a polishing process is performed to form an S/D conductive plug 184, a gate conductive plug 186, and a bridging contact structure 188 in the trench 178a, the trench 176a and the combined trench 180, in accordance with some embodiments).
With respect to claim 2, Wang discloses, in Figs.1A-11, the semiconductor device, wherein bottom surfaces/(top surfaces) of the source/drain contact (156, 160, 158, 184, 188) and the gate contact (148, 146, 169, 168, 186, 188) are on the same plane (see Fig.8).
With respect to claim 3, Wang discloses, in Figs.1A-11, the semiconductor device, further comprising: a gate insulating layer (146) between the second gate electrode (148) and the second plurality of nanosheets (108’) and between the second gate electrode (148) and the gate contact (168-169), wherein the gate insulating layer (146) contacts the gate contact (see Par.[0051], [0053]-[0054] wherein the gate dielectric layers 146 are made of one or more layers of dielectric materials, such as HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO.sub.1—Al2O.sub.3) alloy, another suitable high-k dielectric material, or a combination thereof; the gate electrode layers 148 are formed on the gate dielectric layer 146. In some embodiments, the gate electrode layers 148 are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof; see Par.[0069]-[0072] wherein the conductive layer 169 is tungsten (W), ruthenium (Ru), molybdenum (Mo), or the like. In some embodiments, the conductive layer 169 is formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes; the barrier layer 168 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another applicable material; see Par.[0086]-[0087] wherein a polishing process is performed to form an S/D conductive plug 184, a gate conductive plug 186, and a bridging contact structure 188 in the trench 178a, the trench 176a and the combined trench 180, in accordance with some embodiments).
With respect to claim 4, Wang discloses, in Figs.1A-11, the semiconductor device, wherein at least part of the insulating pattern (151) is between the source/drain contact (184) and the gate contact (186) (see Fig.8).
With respect to claim 5, Wang discloses, in Figs.1A-11, the semiconductor device, further comprising: a second lower interlayer insulating layer (164) on a bottom surface of the first lower interlayer insulating layer (162); and a bottom via/(portions of 184, 186, 188 within insulating 164) in the second lower interlayer insulating layer (164), the bottom via contacting each of a bottom surface of the source/drain contact and a bottom surface of the gate contact (see Fig.8).
With respect to claim 6, Wang discloses, in Figs.1A-11, the semiconductor device, wherein the bottom via is integrally formed with each of the source/drain contact and the gate contact (see Fig.8).
Moreover, regarding the limitation “integrally formed”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Wang. Therefore, it is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 7, Wang discloses, in Figs.1A-11, the semiconductor device, wherein an upper/(lower) surface of the source/drain contact is lower than a bottom/(top) surface of a lowermost/(uppermost) nanosheet of the second plurality of nanosheets (see Fig.8).
With respect to claim 8, Wang discloses, in Figs.1A-11, the semiconductor device, wherein an upper/(lower) surface of the gate contact (148) is higher/(lower) than an upper/(lower) surface of the source/drain contact (156) (see Fig.8).
With respect to claim 9, Wang discloses, in Figs.1A-11, the semiconductor device, wherein each of the source/drain contact (148) and the gate contact (156) is a single film (see Fig.8).
With respect to claim 10, Wang discloses, in Figs.1A-11, the semiconductor device, wherein the source/drain contact (156) includes a first contact barrier layer (158, 160) forming sidewalls and an upper surface of the source/drain contact, and a first contact filling layer (156) filling a space between parts of the first contact barrier layer, wherein the gate contact includes a second contact barrier layer forming sidewalls and an upper surface of the gate contact, and a second contact filling layer filling a space between a portion of the second contact barrier layer, and wherein the first contact filling layer contacts the second contact filling layer (see Par.[0062] wherein the liner 158 is made of silicon nitride, although any other applicable dielectric may be used as an alternative; the barrier layer 160 is made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used).
With respect to claim 11, Wang discloses, in Figs.1A-11, a semiconductor device comprising: a first lower interlayer insulating layer (162); an insulating pattern (151) extending in a first horizontal direction on an upper surface of the first lower interlayer insulating layer (162) (see Par.[0064]-[0067] wherein an etch stop layer 162 is formed over the S/D contact structure 156 and the mask layers 152, and a dielectric layer 164 is formed over the etch stop layer 162; see Par.[0106]-[0108] wherein the mask layer 151 is made of SiO.sub.2, Si.sub.3N.sub.4, SiON, SiOCN, SiOCH, or the like); a plurality of nanosheets (108’) stacked apart from one another in a vertical direction on the insulating pattern (151); a gate electrode (148) extending in a second horizontal direction/(in-out direction of Fig.8 plane) different from the first horizontal direction on the insulating pattern (151), the gate electrode (148) surrounding the plurality of nanosheets (108’) (see Par.[0038], [0041]-[0042], [0049], [0051]-[0053] wherein the nanostructures 108′ are formed, the gate structures 142 are formed wrapped around the nanostructures 108′; the gate structures 142 wrap around the nanostructures 108′ to form gate-all-around transistor structures in accordance with some embodiments); a source/drain region (136) on at least one side of the gate electrode (108’) on the insulating pattern (151) (see Par.[0043]-[0045] wherein source/drain (S/D) structures 136 are formed in the S/D recesses 130); a source/drain contact (156, 184, 188) penetrating the first lower interlayer insulating layer (162) and the insulating pattern (151) in the vertical direction, the source/drain contact electrically connected to the source/drain region; a gate contact (168-169, 186, 188) penetrating the first lower interlayer insulating layer (162) and the insulating pattern (151) in the vertical direction, the gate contact electrically connected to the gate electrode; a second lower interlayer insulating layer (164) on a bottom surface of the first lower interlayer insulating layer (162); and a bottom via/(portions of 184, 186, 188) in the second lower interlayer insulating layer (164), the bottom via contacting each of a bottom surface of the source/drain contact and a bottom surface of the gate contact, wherein the bottom via is integrally formed with each of the source/drain contact and the gate contact (see Par.[0051], [0053]-[0054] wherein the gate dielectric layers 146 are made of one or more layers of dielectric materials, such as HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO.sub.1—Al2O.sub.3) alloy, another suitable high-k dielectric material, or a combination thereof; the gate electrode layers 148 are formed on the gate dielectric layer 146. In some embodiments, the gate electrode layers 148 are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof; see Par.[0069]-[0072] wherein the conductive layer 169 is tungsten (W), ruthenium (Ru), molybdenum (Mo), or the like. In some embodiments, the conductive layer 169 is formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes; the barrier layer 168 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another applicable material; see Par.[0086]-[0087] wherein a polishing process is performed to form an S/D conductive plug 184, a gate conductive plug 186, and a bridging contact structure 188 in the trench 178a, the trench 176a and the combined trench 180, in accordance with some embodiments).
Moreover, regarding the limitation “integrally formed”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Wang. Therefore, it is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 12, Wang discloses, in Figs.1A-11, the semiconductor device, wherein at least part of the insulating pattern (151) is between the source/drain contact and the gate contact (see Fig.8).
With respect to claim 13, Wang discloses, in Figs.1A-11, the semiconductor device, wherein an upper surface of the gate contact is higher than an upper surface of the source/drain contact (see Fig.8).
With respect to claim 14, Wang discloses, in Figs.1A-11, the semiconductor device, wherein at least a portion of a sidewall of the gate contact contacts the source/drain contact (see Fig.8 wherein the same S/D contact and gate contact 188 is shown).
With respect to claim 15, Wang discloses, in Figs.1A-11, the semiconductor device, wherein the gate contact is spaced apart from the source/drain contact in the first horizontal direction (see Fig.8).
With respect to claim 16, Wang discloses, in Figs.1A-11, the semiconductor device, wherein each of the bottom via, the source/drain contact and the gate contact is a single film (see Fig.8).
With respect to claim 18, Wang discloses, in Figs.1A-11, a semiconductor device comprising: a first lower interlayer insulating layer (162); an insulating pattern (151) extending in a first horizontal direction on an upper surface of the first lower interlayer insulating layer (162) (see Par.[0064]-[0067] wherein an etch stop layer 162 is formed over the S/D contact structure 156 and the mask layers 152, and a dielectric layer 164 is formed over the etch stop layer 162; see Par.[0106]-[0108] wherein the mask layer 151 is made of SiO.sub.2, Si.sub.3N.sub.4, SiON, SiOCN, SiOCH, or the like); a first plurality of nanosheets (108’) stacked apart from one another in a vertical direction on the insulating pattern (151); a second plurality of nanosheets (108’) stacked apart from one another in the vertical direction on the insulating pattern (151), the second plurality of nanosheets (108’) spaced apart from the first plurality of nanosheets (108’) in the first horizontal direction; a third plurality of nanosheets (108’) stacked apart from one another in the vertical direction on the insulating pattern (151), the third plurality of nanosheets (108’) spaced apart from the second plurality of nanosheets in the first horizontal direction (see Par.[0038], [0041]-[0042], [0049], [0051]-[0053] wherein the nanostructures 108′ are formed, the gate structures 142 are formed wrapped around the nanostructures 108′; the gate structures 142 wrap around the nanostructures 108′ to form gate-all-around transistor structures in accordance with some embodiments); a first gate electrode (148) extending in a second horizontal direction different from the first horizontal direction on the insulating pattern (151), the first gate electrode (148) surrounding the first plurality of nanosheets (108’); a second gate electrode (148) extending in the second horizontal direction on the insulating pattern, the second gate electrode (148) surrounding the second plurality of nanosheets, the second gate electrode spaced apart from the first gate electrode in the first horizontal direction; a third gate electrode (148) extending in the second horizontal direction on the insulating pattern, the third gate electrode surrounding the third plurality of nanosheets, the third gate electrode spaced apart from the second gate electrode in the first horizontal direction (see Par.[0051], [0054]-[0055] wherein the interfacial layers 144, the gate dielectric layers 146, and the gate electrode layers 148 are formed, a planarization process such as CMP or an etch-back process may be performed until the ILD layer 140 is exposed); a first source/drain region (136) between the first and second gate electrodes on the insulating pattern; a second source/drain region (136) between the second and third gate electrodes on the insulating pattern (see Par.[0043]-[0045] wherein the S/D structures 136 are made of any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof); an upper interlayer insulating layer (140) covering each of the first and second source/drain regions (see Par.[0045]-[0048] wherein the ILD layer 140 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other applicable low-k dielectric materials); a first source/drain contact (156, 160, 158, 184, 188) penetrating the upper interlayer insulating layer in the vertical direction, the first source/drain contact electrically connected to the first source/drain region; a second source/drain contact (156, 160, 158, 184, 188) penetrating the first lower interlayer insulating layer and the insulating pattern in the vertical direction, the second source/drain contact electrically connected to the second source/drain region; and a gate contact (148, 146, 169, 168, 186) penetrating the first lower interlayer insulating layer and the insulating pattern in the vertical direction, the gate contact electrically connected to the second gate electrode, at least a portion of a sidewall of the gate contact is contacting the second source/drain contact, wherein the second source/drain contact and the gate contact are integrally formed (see Par.[0051], [0053]-[0054] wherein the gate dielectric layers 146 are made of one or more layers of dielectric materials, such as HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO.sub.1—Al2O.sub.3) alloy, another suitable high-k dielectric material, or a combination thereof; the gate electrode layers 148 are formed on the gate dielectric layer 146. In some embodiments, the gate electrode layers 148 are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof; see Par.[0069]-[0072] wherein the conductive layer 169 is tungsten (W), ruthenium (Ru), molybdenum (Mo), or the like. In some embodiments, the conductive layer 169 is formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes; the barrier layer 168 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another applicable material; see Par.[0086]-[0087] wherein a polishing process is performed to form an S/D conductive plug 184, a gate conductive plug 186, and a bridging contact structure 188 in the trench 178a, the trench 176a and the combined trench 180, in accordance with some embodiments).
With respect to claim 19, Wang discloses, in Figs.1A-11, the semiconductor device, further comprising: a sacrificial pattern/(portion of dielectric removed to form trenches 166, 178) penetrating the first lower interlayer insulating layer and the insulating pattern in the vertical direction, the sacrificial pattern connected to the first source/drain region, the sacrificial pattern including a material different from a material of each of the first lower interlayer insulating layer and the insulating pattern (see Par.[0067] wherein as shown in FIGS. 2J-1 and 2J-2, after the dielectric layer 164 is formed, trenches 166 are formed through the etch stop layer 150, the dielectric layer 152, the etch stop layer 162, and the dielectric layer 164; see Par.[0078]-[0081] wherein a first portion of the dielectric layer 164 directly above the S/D contact structure 156 is removed to form a trench 178a).
With respect to claim 20, Wang discloses, in Figs.1A-11, the semiconductor device, further comprising: a second lower interlayer insulating layer (164) on a bottom surface of the first lower interlayer insulating layer; and a bottom via in the second lower interlayer insulating layer, the bottom via contacting each of a bottom surface of the source/drain contact and a bottom surface of the gate contact (see Par.[0064]-[0067] wherein an etch stop layer 162 is formed over the S/D contact structure 156 and the mask layers 152, and a dielectric layer 164 is formed over the etch stop layer 162; see Par.[0106]-[0108] wherein the mask layer 151 is made of SiO.sub.2, Si.sub.3N.sub.4, SiON, SiOCN, SiOCH, or the like).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over wang in view of Chang et al. (US 2022/0052168 A1 hereinafter referred to as “Chang”).
With respect to claim 17, Wang discloses all the claimed limitations of claim 11. Moreover, Wang discloses in Figs.1A-11, the semiconductor device, wherein the source/drain contact includes a first contact barrier layer (158, 160) forming sidewalls and an upper surface of the source/drain contact, and a first contact filling layer (156) filling a space between parts of the first contact barrier layer (158, 160), wherein the gate contact (148) includes a second contact barrier layer (146) forming sidewalls and an upper surface of the gate contact, and a second contact filling layer filling a space between a portion of the second contact barrier layer. However, wang does not explicitly disclose wherein the bottom via includes a bottom via barrier layer forming sidewalls of the bottom via, and a bottom via filling layer filling a space between a portion of the bottom via barrier layer, and wherein the bottom via filling layer contacts each of the first and second contact filling layers.
Chang discloses, in Figs.1-19, the semiconductor device, wherein the source/drain contact (240, 246) includes a first contact barrier layer (218, 244) forming sidewalls and an upper surface of the source/drain contact, and a first contact filling layer (2200, 246) filling a space between parts of the first contact barrier layer (218, 244), wherein the gate contact (246) includes a second contact barrier layer (244) forming sidewalls and an upper surface of the gate contact, and a second contact filling layer (246) filling a space between a portion of the second contact barrier layer (244), wherein the bottom via/(portion of 246 within 224) includes a bottom via barrier layer (244) forming sidewalls of the bottom via, and a bottom via filling layer filling a space between a portion of the bottom via barrier layer, and wherein the bottom via filling layer contacts each of the first and second contact filling layers (see Fig.16, Par.[0020] wherein a barrier layer 218 are formed in the source/drain contact opening; see Par.[0027] wherein deposition of a second glue layer 244 (shown in FIGS. 16 and 17), deposition of a metal fill layer 246 (shown in FIGS. 16 and 17), and a planarization process to remove excess materials (shown in FIGS. 18 and 19); see Par.[0026] wherein The patterned multi-layer mask layer 240 includes an opening directly over the gate contact opening 238 and the second source/drain contact 2200. The multi-layer mask layer 240 may be a tri-layer having a bottom layer (i.e., a hard mask layer), a middle layer (i.e. a bottom antireflective coating (BARC)) over the bottom layer and a photoresist layer over the middle layer. Using the patterned multi-layer mask layer as an etch mask, the second ILD layer 224 and the first ESL 222 over the second source/drain contact 2200 are etched using a dry etch process until only a thin portion of the first ESL 222 cover the second source/drain contact 2200).
Wang and Chang are analogous art because they are all directed to a transistor via structure, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Wang to include Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the bottom via structure of Wang by including bottom via barrier on sidewalls as taught by Chang in order to utilize the barrier over sidewalls of S/D gate via contacts integrally formed so as scaling down process to generally provides benefits by increasing production efficiency and lowering associated costs as well as enhancing overall electrical conductivity of the device.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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