DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 07/30/2024.
Claims 1-20 are pending. Claims 1, 8, and 15 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for Domestic CON priority details.
Information Disclosure Statement
5. IDS filed on 10/11/2024 has been considered.
Claim language Objections
6. Claims 1-20 are objected to because of language informality:
Claim 1 (line 7), claim 8 (line 12), and claim 15 (line 9) recite “second voltage offset bit” which appears to contain spelling error/ typo and should recite “second voltage offset bin”. See antecedent limitation on first voltage offset bin. Limitation is interpreted as “second voltage offset bin”.
Claims 8, 15 recites “familys” contains grammatical/ spelling error and should recite “families”.
Claims 2, 9, 16 recite “comrpises” contains spelling error and should recite “comprises”
All dependent claims inclusive of claims 1-20 are objected because of language informality.
Correction is required.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-2, 7-9, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wood et al. (US 2013/0132652 A1).
Regarding independent claim 1, Wood teaches a method (operating method of Fig. 1: 100 “system for managing a configuration parameter for non-volatile memory media”, see Fig. 9, para [0038]) comprising:
responsive to detecting a power up event associated with a memory device (para [0183]: “startup operation” and associated background scan), performing, for each block family of a plurality of block families of the memory device (Fig. 7B: LEB0…LEB4 “storage region”), a first calibration operation to obtain a first voltage offset bin for a respective block family (first calibration operation taken as adjusting and setting “media characteristic” read configurations) to obtain a first voltage offset bin (Fig. 7B: 704a-c, block category or bin according to “media characteristic”. See Fig. 9: 902);
storing, in a record of a temporary metadata table (Fig. 7A: 702 “media characteristic repository” table. See Para [0273]: “Table”, para [0275], para [0276]: “dynamic media characteristics” may be stored on temporary basis), the first voltage offset bin for each block family of the plurality of block families (Fig. 7B: 704a-c for each LEB is stored in 702);
performing, for each block family of the plurality of block families (Fig. 8B: LEB0…LEB4 “storage region”), a second calibration operation (second calibration operation taken as adjusting and setting “configuration parameter” read configurations. See Fig. 9: 904-906) with respect to the respective block family to obtain a second voltage offset bit for a respective block family (Fig. 8B: 804a-c, block category or bin according to “configuration parameter”),
wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation (see e.g., para [0181]: “media characteristic” adjustments are mathematical model based, less accurate read configurations. e.g., read offset “configuration parameter” adjustments are more accurate. Also, second calibration uses first calibration to derive further result hence produces more accurate read configurations, see Fig. 9 in context of para [0007]: “…configuration parameter module…determines … configuration parameters based on the plurality of media characteristics from the media characteristic repository...”); and
storing, in a record of a permanent metadata table (Fig. 8A, Fig. 8B: 802 “configuration parameter repository”. See Para [0279]: “Table”, parameters stored and maintained for a set of cells), the second voltage offset bin for each block family of the plurality of block families (Fig. 8B: 804a-c for each LEB is stored in 802).
Regarding claim 2, Wood teaches the method of claim 1, wherein the respective block family comrpises a set of memory pages (para [0276]).
Regarding claim 7, Wood teaches the method of claim 1, detecting the power up event further comprising determining that the power up event is subsequent to an asynchronous power loss event (para [0275]).
Regarding independent claim 8, Wood teaches a system (Fig. 1: 100 “system for managing a configuration parameter for non-volatile memory media”, see para [0038]) comprising:
a memory device (Fig. 1: 110 “non-volatile memory media”); and
a processing device (Fig. 1: 104: “non-volatile memory controller”, see also Fig. 3B: 104) coupled to the memory device (Fig. 1: 110),
the processing device (Fig. 1: 104) to perform operations comprising:
responsive to detecting a power up event associated with a memory device (para [0183]: “startup operation” and associated background scan),
performing, for each block family of a plurality of block families (Fig. 7B: LEB0…LEB4 “storage region”) of the memory device, a first calibration operation (first calibration operation taken as adjusting and setting “media characteristic” read configurations. See Fig. 9: 902) to obtain a first voltage offset bin (Fig. 7B: 704a-c, block category or bin according to “media characteristic”) for a respective block family (para [0183]: media characteristic for each LEB are changed, updated during startup and associated background scan);
storing, in a record of a temporary metadata table (Fig. 7A: 702 “media characteristic repository” table. See Para [0273]: “Table”, para [0276]), the first voltage offset bin for each block family of the plurality of block families (Fig. 7B: 704a-c for each LEB is stored in 702);
performing, for each block family of the plurality of block families (Fig. 8B: LEB0…LEB4 “storage region”), a second calibration operation (second calibration operation taken as adjusting and setting “configuration parameter” read configurations. See Fig. 9: 904-906) with respect to the respective block familys to obtain a second voltage offset bit (Fig. 8B: 804a-c, block category or bin according to “configuration parameter”) for a respective block family (para [0097], para [0183], para [0200]),
wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation (para [0181]: “media characteristic” and adjustments are mathematical model based, less accurate read configurations. e.g., read offset “configuration parameter” adjustments are more accurate. Also, second calibration uses first calibration to derive further result hence produces more accurate read configurations, see Fig. 9 in context of para [0007]: “…configuration parameter module…determines … configuration parameters based on the plurality of media characteristics from the media characteristic repository...”); and
storing, in a record of a permanent metadata table (Fig. 8A: 802 “configuration parameter repository”. See Para [0200]: Lookup Table), the second voltage offset bin for each block family of the plurality of block families (Fig. 8B: 804a-c for each LEB is stored in 802).
Regarding claim 9, Wood teaches the system of claim 8, wherein the respective block family comrpises a set of memory pages (para [0276]).
Regarding claim 14, Wood teaches the system of claim 8, detecting the power up event further comprising determining that the power up event is subsequent to an asynchronous power loss event (para [0275]).
Regarding independent claim 15, Wood teaches a non-transitory computer-readable storage medium comprising instructions that (para [0008], para [0035]: “computer readable medium”. See also para [0287]), when executed by a processing device (Fig. 1: 104: “non-volatile memory controller”, see also Fig. 3B: 104), cause the processing device to perform operations comprising:
responsive to detecting a power up event associated with a memory device (para [0183]: “startup operation” and associated background scan),
performing, for each block family of a plurality of block families of the memory device (Fig. 7B: LEB0…LEB4 “storage region”), a first calibration operation (first calibration operation taken as adjusting and setting “media characteristic” read configurations) to obtain a first voltage offset bin (Fig. 7B: 704a-c, block category or bin according to “media characteristic”) for a respective block family (para [0183]: media characteristic for each LEB are changed, updated during startup and associated background scan);
storing, in a record of a temporary metadata table (Fig. 7A: 702 “media characteristic repository” table. See Para [0273]: “Table”, para [0276]), the first voltage offset bin for each block family of the plurality of block families (Fig. 7B: 704a-c for each LEB is stored in 702);
performing, for each block family of the plurality of block families (Fig. 8B: LEB0…LEB4 “storage region”), a second calibration operation (second calibration operation taken as adjusting and setting “configuration parameter” read configurations) with respect to the respective block familys to obtain a second voltage offset bit (Fig. 8B: 804a-c, block category or bin according to “configuration parameter”) for a respective block family (para [0097], para [0183], para [0200]),
wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation (para [0181]: “media characteristic” and adjustments are mathematical model based, less accurate read configurations. e.g., read offset “configuration parameter” adjustments are more accurate. Also, second calibration uses first calibration to derive further result hence produces more accurate read configurations, see in context of para [0007]: “…configuration parameter module…determines … configuration parameters based on the plurality of media characteristics from the media characteristic repository...”); and
storing, in a record of a permanent metadata table (Fig. 8A: 802 “configuration parameter repository”. See Para [0200]: Lookup Table), the second voltage offset bin for each block family of the plurality of block families (Fig. 8B: 804a-c for each LEB is stored in 802).
Regarding claim 16, Wood teaches the non-transitory computer-readable storage medium of claim 15, wherein the respective block family comrpises a set of memory pages (para [0276]).
.
Double Patenting
10. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
11. Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,073,866 B2. Although the claims at issue are not identical, they are not patentably distinct from each other. See analysis in the following:
Regarding independent claim 1, US 12,073,866 B2 teaches a method comprising (see US 12,073,866 B2: claim 1, lines 1-2. See also claims 1-7):
responsive to detecting a power up event associated with a memory device, performing, for each block family of a plurality of block families of the memory device, a first calibration operation to obtain a first voltage offset bin for a respective block family to obtain a first voltage offset bin; (US 12,073,866 B2: claim 1, lines 5-11 and claim 2, lines 1-2)
storing, in a record of a temporary metadata table, the first voltage offset bin for each block family of the plurality of block families; (US 12,073,866 B2: claim 1, lines 12-14)
performing, for each block family of the plurality of block families, a second calibration operation with respect to the respective block family to obtain a second voltage offset bit for a respective block family, (US 12,073,866 B2: claim 1, lines 15-17)
wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation; and (US 12,073,866 B2: claim 1, lines 17-19)
storing, in a record of a permanent metadata table, the second voltage offset bin for each block family of the plurality of block families. (US 12,073,866 B2: claim 1, lines 23-25)
Regarding claim 2, US 12,073,866 B2 teaches the method of claim 1, wherein the respective block family comrpises a set of memory pages. (US 12,073,866 B2: claim 1, lines 2-3, claim 2, lines 1-2)
Regarding claim 3, US 12,073,866 B2 teaches the method of claim 1, wherein performing the first calibration operation further comprises: (US 12,073,866 B2: claim 3, lines 1-2)
performing a memory access operation on a memory page of the respective block family, (US 12,073,866 B2: claim 3, lines 1-4)
wherein the memory access operation utilizes a voltage offset associated with the first voltage offset bin; and (US 12,073,866 B2: claim 3, lines 3-6)
selecting, among a plurality of voltage offset bins, a voltage offset bin that is associated with a lowest first value of a data state metric. (US 12,073,866 B2: claim 3, lines 7-9)
Regarding claim 4, US 12,073,866 B2 teaches the method of claim 1, wherein performing the second calibration operation further comprises: (US 12,073,866 B2: claim 4, lines 1-2)
performing a memory access operation on a memory page of the respective block family, (US 12,073,866 B2: claim 4, lines 1-4)
wherein the memory access operation utilizes a voltage offset associated with the second voltage offset bin; and (US 12,073,866 B2: claim 4, lines 1-4)
selecting, among a plurality of voltage offset bins, a voltage offset bin that is associated with a lowest first value of a data state metric. (US 12,073,866 B2: claim 4, lines 7-9)
Regarding claim 5, US 12,073,866 B2 teaches the method of claim 1, further comprising: responsive to determining that a bit flag indicating an updated state of at least a portion of the permanent metadata table is set to a first logical state, (US 12,073,866 B2: claim 5, lines 1-4)
utilizing the temporary metadata table for performing a memory access operation. (US 12,073,866 B2: claim 5, lines 4-6)
Regarding claim 6, US 12,073,866 B2 teaches the method of claim 1, further comprising: responsive to determining that a bit flag indicating an updated state of at least a portion of the permanent metadata table is set to a second logical state, (US 12,073,866 B2: claim 6, lines 1-4)
utilizing the permanent metadata table for performing a memory access operation. (US 12,073,866 B2: claim 6, lines 4-6)
Regarding claim 7, US 12,073,866 B2 teaches the method of claim 1, detecting the power up event further comprising determining that the power up event is subsequent to an asynchronous power loss event. (US 12,073,866 B2: claim 7, lines 1-3)
Regarding independent claim 8, US 12,073,866 B2 teaches a system (US 12,073,866 B2: claim 8, lines 1-2. See also claims 8-14) comprising:
a memory device; and a processing device coupled to the memory device, (US 12,073,866 B2: claim 8, lines 1-4).
the processing device to perform operations comprising:
responsive to detecting a power up event associated with a memory device, performing, for each block family of a plurality of block families of the memory device, a first calibration operation to obtain a first voltage offset bin for a respective block family; (US 12,073,866 B2: claim 8, lines 8-11, and claim 9, lines 1-2).
storing, in a record of a temporary metadata table, the first voltage offset bin for each block family of the plurality of block families; (US 12,073,866 B2: claim 8, lines 15-17)
performing, for each block family of the plurality of block families, a second calibration operation with respect to the respective block familys to obtain a second voltage offset bit for a respective block family, (US 12,073,866 B2: claim 8, lines 18-20)
wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation; and (US 12,073,866 B2: claim 8, lines 20-22).
storing, in a record of a permanent metadata table, the second voltage offset bin for each block family of the plurality of block families. (US 12,073,866 B2: claim 8, lines 26-28)
Regarding claim 9, US 12,073,866 B2 teaches the system of claim 8, wherein the respective block family comrpises a set of memory pages. (see similar analysis like above using US 12,073,866 B2: claim 9 and claim 8)
Regarding claim 10, US 12,073,866 B2 teaches the system of claim 8, wherein performing the first calibration operation further comprises: performing a memory access operation on a memory page of the respective block family, wherein the memory access operation utilizes a voltage offset associated with the first voltage offset bin; and selecting, among a plurality of voltage offset bins, a voltage offset bin that is associated with a lowest first value of a data state metric. (see similar analysis like above using US 12,073,866 B2: claim 10)
Regarding claim 11, US 12,073,866 B2 teaches the system of claim 8, wherein performing the second calibration operation further comprises: performing a memory access operation on a memory page of the respective block family, wherein the memory access operation utilizes a voltage offset associated with the second voltage offset bin; and selecting, among a plurality of voltage offset bins, a voltage offset bin that is associated with a lowest first value of a data state metric. (see similar analysis like above using US 12,073,866 B2: claim 11)
Regarding claim 12, US 12,073,866 B2 teaches the system of claim 8, wherein the operations further comprise: responsive to determining that a bit flag indicating an updated state of at least a portion of the permanent metadata table is set to a first logical state, utilizing the temporary metadata table for performing a memory access operation. (see similar analysis like above using US 12,073,866 B2: claim 12)
Regarding claim 13, US 12,073,866 B2 teaches the system of claim 8, wherein the operations further comprise: responsive to determining that a bit flag indicating an updated state of at least a portion of the permanent metadata table is set to a second logical state, utilizing the permanent metadata table for performing a memory access operation. (see similar analysis like above using US 12,073,866 B2: claim 13)
Regarding claim 14, US 12,073,866 B2 teaches the system of claim 8, detecting the power up event further comprising determining that the power up event is subsequent to an asynchronous power loss event (see similar analysis like above using US 12,073,866 B2: claim 14).
Regarding independent claim 15, US 12,073,866 B2 teaches a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising (US 12,073,866 B2: claim 15, lines 1-4, see also claims 15-20):
responsive to detecting a power up event associated with a memory device, performing, for each block family of a plurality of block families of the memory device, a first calibration operation to obtain a first voltage offset bin for a respective block family; (US 12,073,866 B2: claim 15, lines 7-10)
storing, in a record of a temporary metadata table, the first voltage offset bin for each block family of the plurality of block families; (US 12,073,866 B2: claim 15, lines 14-16)
performing, for each block family of the plurality of block families, a second calibration operation with respect to the respective block familys to obtain a second voltage offset bit for a respective block family, (US 12,073,866 B2: claim 15, lines 17-19)
wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation; and (US 12,073,866 B2: claim 15, lines 19-21)
storing, in a record of a permanent metadata table, the second voltage offset bin for each block family of the plurality of block families. (US 12,073,866 B2: claim 15, lines 25-27)
Regarding claim 16, US 12,073,866 B2 teaches the non-transitory computer-readable storage medium of claim 15, wherein the respective block family comrpises a set of memory pages. (see similar analysis like above using US 12,073,866 B2: claim 15 and claim 16)
Regarding claim 17, US 12,073,866 B2 teaches the non-transitory computer-readable storage medium of claim 15, wherein performing the first calibration operation further comprises:
performing a memory access operation on a memory page of the respective block family, wherein the memory access operation utilizes a voltage offset associated with the first voltage offset bin; and
selecting, among a plurality of voltage offset bins, a voltage offset bin that is associated with a lowest first value of a data state metric.
(see similar analysis like above using US 12,073,866 B2: claim 17)
Regarding claim 18, US 12,073,866 B2 teaches the non-transitory computer-readable storage medium of claim 15, wherein performing the second calibration operation further comprises:
performing a memory access operation on a memory page of the respective block family, wherein the memory access operation utilizes a voltage offset associated with the second voltage offset bin; and
selecting, among a plurality of voltage offset bins, a voltage offset bin that is associated with a lowest first value of a data state metric.
(see similar analysis like above using US 12,073,866 B2: claim 18)
Regarding claim 19, US 12,073,866 B2 teaches the non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: responsive to determining that a bit flag indicating an updated state of at least a portion of the permanent metadata table is set to a first logical state, utilizing the temporary metadata table for performing a memory access operation. (see similar analysis like above using US 12,073,866 B2: claim 19)
Regarding claim 20, US 12,073,866 B2 teaches the non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: responsive to determining that a bit flag indicating an updated state of at least a portion of the permanent metadata table is set to a second logical state, utilizing the permanent metadata table for performing a memory access operation. (see similar analysis like above using US 12,073,866 B2: claim 20)
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Sheperek et al. (US 2021/0191617 A1) is applicable for claim rejections. Sheperek teaches a system (para [0026] and Fig. 1: 100) comprising: a memory device (Fig. 1: 110); and a processing device (“block family manager” in “memory sub-system controller”. See Fig. 5: 510, Fig. 1: 115) coupled to the memory device (Fig. 1: 110),
the processing device (Fig. 5: 510, Fig. 1: 115, Abstract) to perform operations comprising:
identifying a set of memory pages (“block” with “set of pages”) that have been programmed within a time window (para [0054]);
responsive to detecting a power up event (para [0054]: “initialization” block family which triggers detecting “time” difference. See also para [0053]. Also, power loss event can cause charge loss described in Fig. 3, para [0019] and can be used to trigger calibration as understood by ordinary skill in the art), performing a first calibration operation (generation process of Fig. 7: 720) with respect to the set of memory pages to determine a first value of a data state metric (Fig. 7: 720. See para [0023], para [0050]);
identifying, among a plurality of voltage offset bins, a first voltage offset bin corresponding to the first value of the data state metric (para [0062] and Fig. 7: 720 bins. See also para [0048], para [0050]-para [0051], see Fig. 3: 330A, 330B. See also Fig. 4);
storing, in a temporary metadata table (Fig. 7: “Family Table”), a first record associating the set of memory pages with the first voltage offset bin (para [0060]-para [0062]);
performing a second calibration operation (generation process of Fig. 7: 730) with respect to the set of memory pages to determine a second value of the data state metric (para [0063] and Fig. 7: 730 bins),
wherein a second accuracy (see Binned data granularity) of the second calibration operation exceeds a first accuracy of the first calibration operation (see Fig. 7: 720 vs. 730. See binned data granularity of second calibration coverage);
identifying, among a plurality of voltage offset bins, a second voltage offset bin corresponding to the second value of the data state metric (para [0063]); and
storing, in a permanent metadata table, a record associating the set of memory pages with the second voltage offset bin (Fig. 7 in context of para [0063]).
Sheperek teaches the system of claim 8, wherein the set of memory pages is a block family (para [0050], para [0051]).
Sheperek teaches the system of claim 8, detecting the power up event further comprising determining that the power up event is subsequent to an asynchronous power loss event (asynchronous power loss event can cause charge loss described in Fig. 3, para [0019] and can be used to trigger calibration as understood by ordinary skill in the art).
FISHER (US 2019/0043588 A1): Fig. 1A-Fig. 8C applicable for all claims.
Kientz et al. (US 2023/0266904 A1) claims 1-20 are applicable for ODP double patenting rejection and may be used in future for such purposes.
Allowable Subject Matter
Claims 3-6, 10-13, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Further, any associated ODP double patenting rejection (see section 11 above) and claim language objection (see section 6 above) must be over-come.
All claims 1-20 are rejected for ODP double patenting rejections. Thus, all claims are objected to because of the ODP double patenting rejection (see section 11 above).
Regarding claims listed above, the prior art of record Wood et al. does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims 3-6, 10-13, and 17-20.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825