Prosecution Insights
Last updated: April 19, 2026
Application No. 18/788,730

MIXED-MODE VIRTUAL BLOCK GENERATION

Non-Final OA §112
Filed
Jul 30, 2024
Examiner
PHAM, LY D
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
956 granted / 1018 resolved
+25.9% vs TC avg
Minimal +3% lift
Without
With
+3.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
17 currently pending
Career history
1035
Total Applications
across all art units

Statute-Specific Performance

§101
7.2%
-32.8% vs TC avg
§103
22.3%
-17.7% vs TC avg
§102
39.4%
-0.6% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1018 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 – 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1, 3, and 8 – 14 include language considered to be Product and Process in the same claim. A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 USC 112(b). See MPEP section 2173.05(p), II. Presently, claim 1 is drawn to a system, comprising a set of memory components and at least one processing device. The claim also includes methods steps of “identifying…”, “determining…”, “determining…”, and “generating…”. The LANGUAGE of the operation steps that the processing device performs is considered method steps language. Applicant is suggested to amend the claims (as example in claim 1) to include language as follow, … the at least one processing device being configured to: identify a region…; determine that …; determine that …; generate a virtual block…. Similarly, claims 3 and 8 – 14 also need to be amended. Claims 2 and 4 – 7 are also rejected for being dependent to rejected claim 1. Appropriate corrections/revisions are required in order to overcome this type of rejection. Allowable Subject Matter Claims 15 – 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior arts of record fail to teach or reasonably suggest a method comprising, in combination: identifying a region of a set of memory components, the region comprising a plurality of planes across a plurality of decks of the set of memory components; determining that a first memory block within a first deck of the plurality of decks of the region associated with a first plane of the plurality of planes is a first partial good block (PGB), the first PGB including a first portion categorized as being defective and a second portion categorized as being non-defective; determining that a second memory block within the region associated with a second plane of the plurality of planes is a full block (FB), the FB being categorized as non-defective; and generating a virtual block using the first PGB of the first memory block associated with the first plane and a portion of the FB of the second memory block associated with the second plane. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LY D. PHAM Examiner Art Unit 2827 /LY D PHAM/Primary Examiner, Art Unit 2827 February 18, 2026
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Prosecution Timeline

Jul 30, 2024
Application Filed
Feb 23, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MEMORY DEVICE, AND MEMORY SYSTEM AND OPERATION METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
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2y 5m to grant Granted Apr 07, 2026
Patent 12593433
METHOD OF FABRICATING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12592294
APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12586622
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2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.4%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 1018 resolved cases by this examiner. Grant probability derived from career allow rate.

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