DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 9, 11-12, & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2014/0361358) [Hereinafter Chen] & Ahn et al. (KR 100368303B1) [Hereinafter Ahn].
Regarding claim 1, Chen teaches A non-volatile memory device, comprising:
a substrate [fig. 1B, substrate 100, para 22]; and
a memory cell [fig. 1B, para 22, “nonvolatile memory cell unit”], comprising:
a select transistor [fig. 1B, select transistor 20, para 23], comprising
a select gate structure [fig. 1B, select gate 220, para 23] over the substrate (fig. 1B, 100),
a first source/drain region [fig. 1B, 202, para 23] on a first side (left side) of the select gate structures (fig. 1, 220) and
a second source/drain region [fig. 1B, 204, para 23] on a second side (right side) of the select gate structure (fig. 1, 220) opposite the first side;
a floating gate transistor [fig. 1B, floating gate transistor 30, para 24], comprising
a floating gate structure [fig. 1B, floating gate 320, para 24] over the substrate (fig. 1B, 100),
the second source/drain region (fig. 1B, 204) on a third side (left side) of the floating gate structures (fig. 1B, 320) and
a third source/drain region [fig. 1B, source doping region 402, para 25] on a fourth side (right side) of the floating gate structure (fig. 1, 320) opposite the third side (left side).
Chen fails to explicitly disclose a metal conductor over and electrically isolated from the floating gate structure,
wherein the floating gate transistor further comprises
a first low-voltage lightly doped drain between the floating gate structure and the third source/drain region.
However, Ahn teaches a metal conductor [fig. 1F, metal wiring 19, para 26] over and electrically isolated [fig. 1F, isolated by dielectric film 15] from the floating gate structure [fig. 1F, floating gate 12a, para 4],
wherein the floating gate transistor further comprises
a first low-voltage lightly doped drain [fig. 1F, LDD region 14, para 5] between the floating gate structure (fig. 1F, 12a) and the third source/drain region [fig. 1F, source/drain 17, para 7].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the floating gate structure to comprise lightly doped drains to lengthen the depletion region and minimize peak electric field and leakage.
Regarding claim 9, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1, further comprising:
a dielectric layer [Ahn, fig. 1F, dielectric film 15, para 22] fully covering and in contact with a top surface of the floating gate structure (Ahn, fig. 1F, 12a).
Regarding claim 11, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1,
wherein the substrate (Chen, fig. 1B, 100) has a p-type well [Chen, fig. 1B, PW 102/104],
wherein the first (Chen, fig. 1B, 202), second (Chen, fig. 1B, 204), and third source/drain (Chen, fig. 1B, 402) regions have n-type dopants and are disposed in the p-type well [Chen, fig. 1B].
Regarding claim 12, Chen/Ahn teaches the non-volatile memory device as claimed in claim 11,
wherein the substrate further comprises a deep n-type well [Chen, fig. 1C, DNW 510, para 28], wherein the p-type well [Chen, fig. 1C, PW1/PW2/PW] is formed in the deep n- type well.
Regarding claim 15, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1,
wherein the metal conductor (Ahn, fig. 1F, 19) fully covers and overlaps the floating gate structure (Ahn, fig. 1F, 12a).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen & Ahn as applied to claims 1, 9, 11-12, & 15 and further in view of Sun et al. (US 2015/0091080) [Hereinafter Sun].
Regarding claim 10, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
Chen/Ahn fails to explicitly disclose wherein a length of the floating gate structure in a Y-direction is less than a length of the select gate structure in the Y-direction.
However, Sun teaches wherein a length of the floating gate structure [fig. 3, memory gate 281, para 28 & claim 8] in a Y-direction is less than a length of the select gate structure [fig. 3, select gate, para 28 & claim 8] in the Y-direction. [Claim 8 specifically states “wherein a length of the select gate is greater than or equal to a length of the memory gate.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the floating gate to be less than the length of the select gate to optimize cell area and improve switching control.
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen & Ahn as applied to claims 1, 9, 11-12, & 15 and further in view of Wang et al. (US 6580642).
Regarding claim 16, Chen/Ahn teaches The non-volatile memory device as claimed in claim 1.
Chen/Ahn fails to explicitly disclose wherein the memory cell is programmed by inducing channel hot electron injection under the floating gate structure.
However, Wang teaches wherein the memory cell is programmed by inducing channel hot electron injection under the floating gate structure. [para 5, “The tunneling injector memory cell 1 is programmed and erased by injection of electrons and holes respectively on the floating gate.”].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to utilize hot electron injection for programming to enable fast programming speeds compared to other methods.
Regarding claim 17, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
Chen/Ahn fails to explicitly disclose wherein the memory cell is erased by inducing band-to-band hot hole injection under the floating gate structure.
However, Wang teaches wherein the memory cell is erased by inducing band-to-band hot hole injection under the floating gate structure. [para 5, “The tunneling injector memory cell 1 is programmed and erased by injection of electrons and holes respectively on the floating gate.”].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to utilize band to band hot hole injection to achieve fast, localized erasure using low gate voltages.
Allowable Subject Matter
Claims 2-8 & 13-14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
The prior art of record fails to explicitly disclose in entirety wherein the floating gate transistor further comprises:
a first medium-voltage lightly doped drain between the floating gate structure and the second source/drain region,
wherein the select transistor further comprises:
a second medium-voltage lightly doped drain between the select gate structure and the second source/drain region; and
a third medium-voltage lightly doped drain between the select gate structure and the first source/drain region,
wherein dopant concentrations of the first, second, and third medium-voltage lightly doped drains are lower than a dopant concentration of the first low-voltage lightly doped drain.
Thereby claim 2 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 contains allowable subject matter based upon dependency on claim 2.
Regarding claim 4, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
The prior art of record fails to explicitly disclose in entirety wherein the floating gate transistor further comprises:
a second low-voltage lightly doped drain between the floating gate structure and the second source/drain region,
wherein the select transistor further comprises:
a first medium-voltage lightly doped drain between the select gate structure and the second source/drain region; and
a second medium-voltage lightly doped drain between the select gate structure and the first source/drain region,
wherein dopant concentrations of the first and second medium-voltage lightly doped drains are lower than dopant concentrations of the first and second low-voltage lightly doped drains.
Thereby claim 4 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 contains allowable subject matter based upon dependency on claim 4.
Regarding claim 6, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
The prior art of record fails to explicitly disclose in its entirety wherein the floating gate transistor further comprises: a second low-voltage lightly doped drain between the floating gate structure and the second source/drain region, wherein the select transistor further comprises:
a third low-voltage lightly doped drain between the select gate structure and the second source/drain region; and
a medium-voltage lightly doped drain between the select gate structure and the first source/drain region,
wherein a dopant concentration of the medium-voltage lightly doped drain is lower than dopant concentrations of the first, second, and third low-voltage lightly doped drains.
Thereby claim 6 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 contains allowable subject matter based upon dependency on claim 6.
Regarding claim 8, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
The prior art of record fails to explicitly disclose in entirety wherein the floating gate transistor further comprises:
a second low-voltage lightly doped drain between the floating gate structure and the second source/drain region,
wherein the select transistor further comprises:
a third low-voltage lightly doped drain between the select gate structure and the second source/drain region; and
a fourth low-voltage lightly doped drain between the select gate structure and the first source/drain region.
Thereby claim 8 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 13, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
The prior art of record fails to explicitly disclose in entirety wherein when the memory cell is programmed,
the p-type well is connected to ground,
the select gate structure is connected to a first positive voltage,
the floating gate structure is floating,
the first source/drain region is connected to ground,
the metal conductor is connected to a second positive voltage, and
the third source/drain region is connected to a third positive voltage,
wherein the second positive voltage is greater than or equal to the third positive voltage.
Thereby claim 13 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 14, Chen/Ahn teaches the non-volatile memory device as claimed in claim 1.
The prior art of record fails to explicitly disclose in entirety wherein when the memory cell is erased,
the p-type well is connected to ground,
the select gate structure is connected to ground,
the floating gate structure is floating,
the first source/drain region is connected to ground,
the metal conductor is connected to a negative voltage, and
the third source/drain region is connected to a positive voltage.
Thereby claim 14 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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