DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 07/30/2024.
Claims 1-20 are pending. Claims 1, 8, and 15 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority is in the record.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 07/30/2024. This IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 101
6. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
7. Claims 8-14 are rejected under 35 U.S.C 101 as being directed to a nonstatutory subject matter because the recited “tangibly embodied in a machine-readable storage device” (in claim 8 and associated dependents) is not within one of the four statutory categories and the body of the claim is not within one of the four statutory categories.
Further, the broadest reasonable interpretation of “machine-readable storage device” is a transitory propagating signal per se. The language “tangibly embodied” is not sufficient or does not teach non-transitory CRM. Specification para [0016], [00101] was scrutinized and the spec also does not use clear language to define “non-transitory” machine-readable storage device. See Subject Matter Eligibility of Computer Readable Media, 1351 OG 212 (February 23, 2010).
Signals per se are ineligible. see MPEP 2106 (I).
Also, this claim is drawn to a "computer program" stored on the computer readable medium. The act of storing a program on a computer readable medium does not amount to something significantly more than the program because storing computer files on computer disks was well-understood, routine, and conventional activity previously known in the industry. See Alice Corp. v. CLS Bank Int’l, 573 U.S. (2014) (slip op., at 15). Indeed, the computer readable medium provision is a mere drafting effort that eviscerates the judicial exceptions. Alice (slip op., at 14). A computer program per se, such as the one claimed, is ineligible. see MPEP 2106(I).
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bronson et al. (US 2009/0106607 A1).
Regarding independent claim 1, Bronson teaches an integrated circuit (para [0025]: “…SC chip…IBM Z6 computer system…”), comprising:
a semiconductor substrate (in context of para [0025]: “chip” substrate);
integrated circuitry on the semiconductor substrate (Fig. 2A-2B in context of para [0025]: SRAM memory),
wherein the integrated circuitry includes a memory array (para [0025]: SRAM memory and array) including:
a plurality of memory macros including at least first (Fig. 2A-2B: any “interleave” group of “SRAM macros”. See para [0018], para [0025], Abstract) and second memory macros (group of “spare SRAM macros”. See para [0018], para [0025], Abstract, Fig. 3A-3B), wherein
each of the plurality of memory macros (each “interleave” group and each group of “spare SRAM macros”) includes:
multiple partial arrays (each “interleave” group has 12 “SRAM macro” array and each group of “spare SRAM macros” has 2 “spare SRAM macro” array. Claim does not further describe partial array and is taken as an array which is part of a group of arrays); and
a shared macro controller (para [0028]: “main cache controller”) configured to control read and write access to the multiple partial arrays (para [0028]); and
spare access control logic (“sparing configuration register” and “main interleave controller” combined) configured to direct an access to a first partial array in the first memory macro to a second partial array in the second memory macro (“…macro sparing in accordance with the invention technically allows a defective or failed SRAM macro to be shut off and replaced by a spare macro…”, see e.g. para [0009], abstract, para [0018], para [0025], para [0030]).
Regarding claim 2, Bronson teaches the integrated circuit of claim 1, wherein: the plurality of memory macros includes a third memory macro (Fig. 2A-2B: any second “interleave” group of “SRAM macros”); and
the spare access control logic is configured to direct an access to a third partial array in the third memory macro to a fourth partial array in the second memory macro (see e.g. para [0009], abstract, para [0018], para [0025], para [0030]).
Regarding claim 3, Bronson teaches the integrated circuit of claim 1, further comprising: an array built-in self-test (ABIST) circuit (“ABIST engine”, see e.g. para [0025]) configured to replace the first partial array with the second partial array (see para [0025]-para [0026], para [0028]).
Regarding claim 4, Bronson teaches the integrated circuit of claim 3, wherein: the integrated circuit includes at least one configuration register (para [0030]: “sparing configuration registers”); and the ABIST circuit replaces the first partial array with the second partial array by updating the at least one configuration register (Fig. 5 in context of para [0030, para [0028])].
Regarding claim 5, Bronson teaches the integrated circuit of claim 1, wherein: the access is a read access; the memory array includes a read data return bus having a plurality of data beats (para [0027], para [0030] and Fig. 5A-5B, Fig. 4A-4B disclosure), wherein the first partial array is assigned a particular data beat among the plurality of data beats (para [0027], para [0030] and Fig. 5A-5B, Fig. 4A-4B disclosure); the spare access control logic is configured to cause the second partial array to drive read data on the read data return bus during the particular data beat (para [0027], para [0030] and Fig. 5A-5B, Fig. 4A-4B disclosure).
Regarding claim 6, Bronson teaches the integrated circuit of claim 1, wherein each of the plurality of memory macros includes a row address decoder shared by the multiple partial arrays (para [0005]: control circuitry and means).
Regarding claim 7, Bronson teaches the integrated circuit of claim 1, wherein the memory array comprises an embedded static random-access memory (SRAM) (see para [0003], para [0006]: embedded SRAM).
Regarding independent claim 8, Bronson teaches a design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit (machine-readable storage device is conventional item used conventionally to store computer programs, design algorithm to perform generic computer functions that are well-understood, routine, and conventional activities previously known to the pertinent industry, and several court cases demonstrate that the mere recitation of a generic system and computer algorithm cannot transform a general idea into a patent-eligible invention),
the design structure comprising:
an integrated circuit (para [0025]: “…SC chip…IBM Z6 computer system…”), including:
a semiconductor substrate (in context of para [0025]: “chip” substrate);
integrated circuitry on the semiconductor substrate (Fig. 2A-2B in context of para [0025]: SRAM memory),
wherein the integrated circuitry includes a memory array (para [0025]: SRAM memory and array) including:
a plurality of memory macros including at least first (Fig. 2A-2B: any “interleave” group of “SRAM macros”. See para [0018], para [0025], Abstract) and second memory macros (group of “spare SRAM macros”. See para [0018], para [0025], Abstract, Fig. 3A-3B),
wherein each of the plurality of memory macros (each “interleave” group and each group of “spare SRAM macros”) includes:
multiple partial arrays (each “interleave” group has 12 “SRAM macro” array and each group of “spare SRAM macros” has 2 “spare SRAM macro” array. Claim does not further describe partial array and is taken as an array which is part of a group of arrays); and
a shared macro controller (para [0028]: “main cache controller”) configured to control read and write access to the multiple partial arrays (para [0028]); and
spare access control logic (“sparing configuration register” and “main interleave controller” combined) configured to direct an access to a first partial array in the first memory macro to a second partial array in the second memory macro (“…macro sparing in accordance with the invention technically allows a defective or failed SRAM macro to be shut off and replaced by a spare macro…”, see e.g. para [0009], abstract, para [0018], para [0025], para [0030]).
Regarding claim 9, Bronson teaches the design structure of claim 8, wherein: the plurality of memory macros includes a third memory macro (Fig. 2A-2B: any second “interleave” group of “SRAM macros”); and the spare access control logic is configured to direct an access to a third partial array in the third memory macro to a fourth partial array in the second memory macro (see e.g. para [0009], abstract, para [0018], para [0025], para [0030]).
Regarding claim 10, Bronson teaches the design structure of claim 8, further comprising: an array built-in self-test (ABIST) circuit configured to replace the first partial array with the second partial array (see para [0025]-para [0026], para [0028]).
Regarding claim 11, Bronson teaches the design structure of claim 10, wherein: the integrated circuit includes at least one configuration register; and the ABIST circuit replaces the first partial array with the second partial array by updating the at least one configuration register (see para [0025]-para [0026], para [0028]).
Regarding claim 12, Bronson teaches the design structure of claim 8, wherein: the access is a read access; the memory array includes a read data return bus having a plurality of data beats, wherein the first partial array is assigned a particular data beat among the plurality of data beats; the spare access control logic is configured to cause the second partial array to drive read data on the read data return bus during the particular data beat (para [0027], para [0030] and Fig. 5A-5B, Fig. 4A-4B disclosure).
Regarding claim 13, Bronson teaches the design structure of claim 8, wherein each of the plurality of memory macros includes a row address decoder shared by the multiple partial arrays (para [0005]: control circuitry and means).
Regarding claim 14, Bronson teaches the design structure of claim 8, wherein the memory array comprises an embedded static random-access memory (SRAM) (see para [0003], para [0006]).
Regarding independent claim 15, Bronson teaches a method of operating a memory array (See Abstract: method of SRAM macro sparing), comprising:
in a memory array (Fig. 2A-2B, para [0025]: SRAM memory and array) including a plurality of memory macros including at least first (Fig. 2A-2B: any “interleave” group of “SRAM macros”. See para [0018], para [0025], Abstract) and second memory macros (group of “spare SRAM macros”. See para [0018], para [0025], Abstract, Fig. 3A-3B),
wherein each of the plurality of memory macros (each “interleave” group and each group of “spare SRAM macros”) includes:
multiple partial arrays (each “interleave” group has 12 “SRAM macro” array and each group of “spare SRAM macros” has 2 “spare SRAM macro” array. Claim does not further describe partial array and is taken as an array which is part of a group of arrays); and
a shared macro controller (para [0028]: “main cache controller”) configured to control read and write access to the multiple partial arrays (para [0028]),
replacing the first partial array in the first memory macro with a second partial array in the second memory macro in a partial sparing event (“…macro sparing in accordance with the invention technically allows a defective or failed SRAM macro to be shut off and replaced by a spare macro…”, see e.g. para [0009], abstract, para [0018], para [0025], para [0030]).; and
thereafter, a spare access control circuit in the memory array directing an access to the first partial array in the first memory macro to the second partial array in the second memory macro (see e.g. para [0009], abstract, para [0018], para [0025], para [0030]).
Regarding claim 16, Bronson teaches the method of claim 15, wherein: the plurality of memory macros includes a third memory macro Fig. 2A-2B: any second “interleave” group of “SRAM macros”); and the method further includes: replacing a third partial array in a third memory macro with a fourth partial array in the second memory macro in a partial sparing event (see e.g. para [0009], abstract, para [0018], para [0025], para [0030]); and thereafter, the spare access control circuit directing an access to the third partial array in the third memory macro to the fourth partial array in the second memory macro (see e.g. para [0009], abstract, para [0018], para [0025], para [0030]).
Regarding claim 17, Bronson teaches the method of claim 15, wherein the replacing includes: an array built-in self-test (ABIST) circuit replacing the first partial array with the second partial array (see para [0025]-para [0026], para [0028]).
Regarding claim 18, Bronson teaches the method of claim 17, wherein: the integrated circuit includes at least one configuration register; and the replacing includes the ABIST circuit updating the at least one configuration register (Fig. 5 in context of para [0030, para [0028]).
Regarding claim 19, Bronson teaches the method of claim 15, wherein: the access is a read access; the memory array includes a read data return bus having a plurality of data beats, wherein the first partial array is assigned a particular data beat among the plurality of data beats; the method further includes the spare access control circuit causing the second partial array to drive read data on the read data return bus during the particular data beat (para [0027], para [0030] and Fig. 5A-5B, Fig. 4A-4B disclosure).
Regarding claim 20, Bronson teaches the method of claim 15, wherein: each of the plurality of memory macros includes a row address decoder shared by the multiple partial arrays (para [0005]: control circuitry and means); and the method further comprises the row address decoder, based on the access, asserting a wordline shared by the multiple partial arrays (This limitation is general and commonly known in the art; disclosed apparatus and configuration teaches this limitation).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Bronson (US 2020/0264803 A1): Fig. 1-Fi. 6 disclosure applicable.
Lee (US 2002/0109154 A1): Lee teaches a semiconductor memory device (Fig. 3 “memory device”, see para [0013]) comprising: a memory cell array (para [0013] and Fig. 3: memory cells in array) including a plurality of memory blocks (Fig. 3: 31, 32, 33 “blocks”) coupled to at least one word-line (word lines with memory cells in array), wherein each of the plurality of memory blocks includes a plurality of dynamic memory cells; at least one bit-line switch (e.g. Fig. 5: S22’s, S23’s) connected between a first half local input/output (I/O) line (Fig. 3, Fig. 5: LIO2L) of a first memory block of the plurality of memory blocks (Fig. 3 32L, see Fig. 5 LIO2L connection) and a second half local I/O line (Fig. 3, Fig. 5 LIO2R) of the first memory block (Fig. 3: 32R, see Fig. 5 LIO2R connection), wherein the first half local I/O line of the first memory block (see Fig. 3: 32L) is connected to a first group of bit-lines of a plurality of bit-lines of the first memory block (Fig. 3: bitlines associated with CSL’s and SCSL’s in 32L. See also Fig. 5), and the second half local I/O line of the first memory block (see Fig. 3: 32R) is connected to a second group of bit-lines of the plurality of bit-lines (Fig. 3: bitlines associated with CSL’s and SCSL’s in 32R. see also Fig. 5); at least one block switch (Fig. 3 in context of para [0029]: “switches” establishing path1, path2) connected between the second half local I/O line of the first memory block (Fig. 3: 32L) and a first half local I/O line of a second memory block (Fig. 3: 31R) among the plurality of memory blocks (Fig. 3 repair scheme in context of para [0027], para [0022]: see repair operation between 32R and 33L), wherein the first memory block and the second memory block are adjacent to each other (Fig. 3: 32, 33 are adjacent); and
a column decoder including a repair circuit (para [0035]: “switching controller”, see also para [0039]), wherein the repair circuit is configured to control a connection (connected for repair or replacement, see Fig. 5) between the first half local I/O line of the first memory block (Fig. 3: 32L, see also Fig. 5) and the second half local I/O line of the first memory block (Fig. 3: 32R, see also Fig. 5) by applying a first switching control signal (para [0039]: switch control signals) to the at least one bit-line switch (e.g. Fig. 5: S22’s and S23’s), and is configured to control a connection between the second half local I/O line of the first memory block (Fig. 3: 32R) and the first half local I/O line of the second memory block (Fig. 3: 33L) by applying a second switching control signal to the at least one block switch (para [0027], para [0022]. See also para [0030], para [0039]).
KIM et al. (US 2019/0096508 A1): See abstract and figures applicable for all claims. CHO et al. (US 2019/0348140 A1): See abstract and figures applicable for all claims.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825