DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 5 has been cancelled.
Response to Arguments
Applicant’s arguments (hereinafter “arguments”), see pages 3-4, filed 5/15/2026, with respect to the rejection(s) of claim(s) 1, 10 and 17 under 35 USC 102 and/or 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20220223787 to Pinarbasi et al. (“Pinarbasi”), US 20240147868 to Mizusaki et al. (“Mizusaki”) and US 20250384928 to Ambrosi et al. (“Ambrosi”).
The arguments allege that the teachings of the preciously cited prior art do not include newly introduced subject matter into independent claim(s) 1, 10 and 17.
As to claim 1, the arguments allege that “wherein the apparatus is configured as an L1/L2 cache” is not disclosed in the previously cited prior art. Without conceding in the least that such allegations are grounded in fact, at the very least the teachings of Pinarbasi obviate this newly new claim limitation: in the relevant art of SOT/MTJ memory/storage devices, the teachings of Pinarbasi in at least [0005] provide: Spin orbit torque based MRAM devices show switching speeds down to about 200 ps, making them usable for L1/L2 cache applications. Such teachings also provide grounds for art combination: switching speeds down to about 200 ps.
As to claim 10, the arguments allege that “wherein the method is performed in response to a host-device command” is not disclosed in the previously cited prior art. Without conceding in the least that such allegations are grounded in fact, at the very least the teachings of Mizusaki obviate this newly new claim limitation: in the relevant art of SOT/MTJ memory/storage devices, the teachings of Mizusaki in at least [0105]-[0107] provide: host/processor command-based accessing of SOT/MTJ memory. That a host/processor command-based memory access could be a novel claim is akin to claiming that a generic memory device is a novel invention. It is well-known, well-understood that memory devices are passive devices: they need host/processor interaction to receive/transmit data.
As to claim 17, the arguments allege that “and a controller configured to activate one or more rows corresponding to a page of stored data, and to read states of MTJs in memory cells of the activated one or more rows” is not disclosed in the previously cited prior art. Without conceding in the least that such allegations are grounded in fact, at the very least the teachings of Ambrosi obviate this newly new claim limitation: in the relevant art of SOT/MTJ memory/storage devices, the teachings of Ambrosi in at least [0021], [0025] provide: “The memory array 101 comprises a plurality of memory cells MC arranged in a plurality of columns and rows of the corresponding memory array. The memory array 101 further comprises a plurality of word lines (also referred to as “address lines”) extending along a row direction (i.e., the horizontal direction in FIG. 1A) of the rows, and a plurality of bit lines (also referred to as “data lines”) extending along a column direction (i.e., the vertical direction in FIG. 1A) of the columns. The memory controller 120 is electrically coupled, by the word lines and/or bit lines, to the memory cells MC and configured to control operations of the memory cells MC including, but not limited to, a read operation.” And, further, “The word line driver 122 is coupled to the memory array 101 via the word lines WL, including the write word lines WWL0 to WWLn and read word lines RWL0 to RWLn. The word line driver 122 is configured to decode a row address of the memory cell MC selected to be accessed in an access operation. The word line driver 122 is sometimes referred to as a word line decoder. The word line driver 122 is configured to supply a voltage to the selected word line WL corresponding to the decoded row address.” Once more, it is well-known and well-understood that accessing or activating rows and columns in a memory device is part and parcel of peripheral logic such as memory controllers which are in communication with the memory and a host/processor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 111354392 A to Yu et al. (“Yu”) in view of US 20220223787 to Pinarbasi et al. (“Pinarbasi”).
As to claim 1, Yu teaches an apparatus comprising: a spin orbit torque (SOT) layer (As found in at least FIG. 1: SOT 501 layer); and at least two magnetic tunnel junctions (MTJs) configured to share the SOT layer (As found in at least FIG. 1: first MTJ 502 and second MTJ 503 share SOT 501).
Yu and Pinarbasi are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory including SOT/MTJ.
Note: Section three (3) above in this Office action is referenced herein fully, and is made integral part of the claim rejection.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Yu as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Pinarbasi also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: relevant memory switching speeds down to about 200 ps.
Therefore, it would have been obvious to combine Yu with Pinarbasi to make the above modification.
As to claim 2, Yu teaches wherein each MTJ is configured to independently store a bit of data (As found in the body of the reference: “The invention claims a new-type magnetic memory array (SOT-MRAM), magnetic storage structure of the array 2 is used in switching transistor (transistor) to drive 2 of magnetic storage unit (MTJ). forming a 2T-2R structure, the magnetic memory structure of the invention can be stored 2 memory bit (bit), and each magnetic memory unit are independently operable and effective set of double memory unit on the unit area, can greatly increase the integration density.”).
As to claim 3, Yu teaches wherein the MTJs comprise first and second MTJs, the apparatus further comprising: a first bitline configured for use in writing a first bit in the first MTJ; and a second bitline configured for use in writing a second bit in the second MTJ (As found in at least FIG. 1: MTJs 502 and 503; first bitline BL1-1 and second bitline BL1-2).
As to claim 4, Yu teaches wherein the first bitline is electrically coupled to a source line by the SOT layer and a transistor, and the second bitline is electrically coupled to the source line by the SOT layer and the transistor (As found in at least FIG. 1: bitline BL1-1 coupled to source line SL1 by SOT 501 and transistor 20; bitline BL1-2 coupled to source line SL1 by SOT 501 and transistor 20).
As to claim 6, Yu teaches further comprising a first transistor configured for independently writing each of first and second MTJs, and a second transistor configured for independently reading each of the first and second MTJs (As found in at least FIG. 1: first transistor 20 for writing each MTJ 502 and 503; second transistor 30 for reading each MTJ 502 and 503).
As to claim 7, Yu teaches wherein the first and second transistors share a common source (As found in at least FIG. 1: 20 and 30 share common source line SL1).
As to claim 8, Yu teaches wherein the first transistor has a drain electrically connected to the SOT layer at a point between the first and second MTJs (As found in at least FIG. 1: 20 has a drain terminal electrically connected to SOT 501 at a point between 502 and 503).
As to claim 9, Yu teaches wherein the second transistor has a drain electrically connected to each of the first and second MTJs (As found in at least FIG. 1: drain terminal of 30 connects to MTJs 502 and 503).
Claim(s) 10-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 111354392 A to Yu et al. (“Yu”) in view of US 20240147868 to Mizusaki et al. (“Mizusaki”) .
As to claim 10, Yu teaches A method comprising: switching on, using a write wordline, a first transistor having a current terminal connected to a spin orbit torque (SOT) layer; switching off, using a read wordline, a second transistor having a current terminal connected to first and second magnetic tunnel junctions (MTJs) that share the SOT layer; and applying a bias to a first bitline coupled to the SOT layer, the bias determining a first state written to the first MTJ (As found in at least FIGS. 1-3 and in the body of the reference: “Specifically, both an NMOS as an example for explanation to the first switch and the second switch, the magnetic memory unit shown in Figure 3, in the dotted line frame 50, when the first bit unit 50a writes "1", the first word line WL1 is applied with the high voltage Vdd to the first switch gating, the second word line RL1 is applied with ground voltage so that the second switch is closed, the second bit line BL1-2 is suspended, the first bit line BL1-1 applying a high voltage Vdd”).
Note: Section three (3) above in this Office action is referenced herein fully, and is made integral part of the claim rejection.
Yu and Mizusaki are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory including SOT/MTJ.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Yu as set forth in this Office action and as found in the reference with the relevant and complementary teachings of MIzusaki also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: It is well-known, well-understood that memory devices are passive devices: they need host/processor interaction to receive/transmit data.
Therefore, it would have been obvious to combine Yu with Mizusaki to make the above modification.
As to claim 11, Yu teaches wherein a second bitline coupled to the SOT layer is floating while the first state is written to the first MTJ (As found in at least FIGS. 1-3 and in the body of the reference: Specifically, both an NMOS as an example for explanation to the first switch and the second switch, the magnetic memory unit shown in Figure 3, in the dotted line frame 50, when the first bit unit 50a writes "1", the first word line WL1 is applied with the high voltage Vdd to the first switch gating, the second word line RL1 is applied with ground voltage so that the second switch is closed, the second bit line BL1-2 is suspended, the first bit line BL1-1 applying a high voltage Vdd”).
As to claim 12, Yu teaches wherein: the write wordline is coupled to a first gate of the first transistor; the read wordline is coupled to a second gate of the second transistor; bias circuitry is configured to bias the write wordline, the read wordline, and the first bitline (As found in at least FIGS. 1-3: write WL1 is coupled to gate of first transistor 20, read RL1 is coupled to gate of second transistor 30; and, as found in the rejection to at least claim 10, WL1, RL1 and BL1-1 are biased; also refer to: “FIG. 1 is a circuit structure …,” “FIG. 3 shows an embodiment of the present invention for writing a magnetic memory array method and reading method of circuit state diagram.”).
As to claim 13, Yu teaches further comprising applying a bias to a second bitline coupled to the SOT layer, the bias determining a second state written to the second MTJ, wherein the first bitline is floating while the second state is written to the second MTJ (As found in at least FIGS. 1-3 and in the body of the reference: “when the second bit unit 50b writes "1", the first word line WL1 is applied with the high voltage Vdd to the first gating switch, the second word line RL1 is applied with ground voltage so that the second switch is closed, the suspended first bit line BL1-1, second bit line BL1-2 applying a high voltage Vdd”).
As to claim 14, Yu teaches further comprising: after the first state is written to the first MTJ, switching off, using the write wordline, the first transistor; switching on, using the read wordline, the second transistor; and applying a bias to the first bitline for reading the first state (As found in at least FIGS. 1-3 and in the body of the reference: “Specifically, when the first bit unit 50a for reading the first word line WL1 is applied with ground voltage so that the first switch is closed, the second word line RL1 applying a high voltage Vdd so that the second switch gating, the second bit line BL1-2 is suspended, the first bit line BL1-1 applying a high voltage Vdd”).
As to claim 15, Yu teaches wherein the first state is determined based on a resistance of the first MTJ (As found in at least FIGS. 1-3 and in the body of the reference: “by reading the magnitude of the output current flowing through the magnetic tunnel junction to determine the resistance state of the magnetic tunnel junction is high resistance or low resistance state”).
As to claim 16, Yu teaches wherein a second bitline coupled to the SOT layer is floating while reading the first state (As found in at least FIGS. 1-3 and in the body of the reference: “Specifically, when the first bit unit 50a for reading the first word line WL1 is applied with ground voltage so that the first switch is closed, the second word line RL1 applying a high voltage Vdd so that the second switch gating, the second bit line BL1-2 is suspended, the first bit line BL1-1 applying a high voltage Vdd”).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 111354392 A to Yu et al. (“Yu”) in view of US 20240147868 to Mizusaki et al. (“Mizusaki”) in view of US 20250384928 to Ambrosi et al. (“Ambrosi”)
As to claim 17, Yu teaches An apparatus comprising: sensing circuitry configured in a semiconductor substrate (As found in at least FIGS. 1-3, there is disclosed an apparatus configured in a semiconductor substrate 10; said apparatus is arranged to be written to and read from, as set forth in this Office action in the rejection to previous claims; reading from such apparatus involves sensing circuitry to sense current through said apparatus; this is made abundantly obvious in the body of the reference, for example: “Specifically, when the first bit unit 50a for reading the first word line WL1 is applied with ground voltage so that the first switch is closed, the second word line RL1 applying a high voltage Vdd so that the second switch gating, the second bit line BL1-2 is suspended, the first bit line BL1-1 applying a high voltage Vdd, source line SL1 applying a ground voltage to sense current flowing through the first bit unit 50a”); a spin orbit torque (SOT) layer overlying the semiconductor substrate (As found in at least FIG. 2: SOT 501 overlaying substrate 10); and at least two magnetic tunnel junctions (MTJs) overlying the SOT layer (As found in at least FIG. 2: MTJs 502 and 503 overlay SOT 501), wherein each MTJ has a free layer in contact with a top surface of the SOT layer (As found in at least FIG. 4: each MTJ, such as 502, has free layer 701 in contact with SOT 501); wherein the sensing circuitry is configured to read a state of each MTJ (As found in at least claim 25 of the reference).
Note: Section three (3) above in this Office action is referenced herein fully, and is made integral part of the claim rejection.
Yu and Ambrosi are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory including SOT/MTJ.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Yu as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Ambrosi also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: it is well-known and well-understood that accessing or activating rows and columns in a memory device is part and parcel of peripheral logic such as memory controllers which are in communication with the memory and a host/processor.
Therefore, it would have been obvious to combine Yu with Ambrosi to make the above modification.
As to claim 18, Yu teaches further comprising a metal layer underlying the SOT layer, wherein the metal layer comprises a first bitline configured to read and write a first MTJ, and a second bitline configured to read and write a second MTJ (As found in at least FIG. 2: bitlines BL1-1 and BL1-2, metal layers underlying SOT 501).
As to claim 19, Yu teaches further comprising: a write transistor configured in the semiconductor substrate, the write transistor having a drain electrically connected to the SOT layer by vertical interconnect (As found in at least FIG. 2: write transistor 104 in substrate 10 whose drain connects SOT 501); and a read transistor configured in the semiconductor substrate, the read transistor having a drain electrically connected to the MTJs by vertical interconnect (As found in at least FIG. 2: read transistor 105 in substrate 10 whose drain connects to MTJs 501 and 503).
As to claim 20, Yu teaches further comprising a source line patterned in a metal layer overlying the semiconductor substrate and underlying the SOT layer, wherein a source of the write transistor and a source of the read transistor are each connected to the source line (As found in at least FIG. 2: source line SL1, metal layer underlying SOT 501 and overlying substrate 10, and source terminal of 104 and 105 connect to source line SL1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights