DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground of rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6-9, and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US Pat. Pub. 2012/0079342; hereinafter referred to as Lu) in view of Pawlowski et al (US Pat. 8,601,341; hereinafter referred to as Pawlowski).
As per claims 1, 6, 14: Lu teaches a method of performing a read operation with a first level error correction code (ECC) circuit and a second level ECC circuit, comprising:
a memory device configured to store a first word of data bits (Fig. 1, 104); and
a memory controller configured to perform a read operation for the first word (Fig. 1, 102);
inputting a first word (Fig. 4, 412) and first level check bits corresponding with the segments (Fig. 4, 414) into a syndrome calculation circuit (paragraph 39 last sentence) of the first level ECC circuit (Fig. 1, 106);
generating, with the syndrome calculation circuit, syndromes for the segments using a transpose of a parity-check matrix (paragraphs 22 and 28) comprising multiplying the segment with the transpose of the parity-check matrix (paragraph 28; last sentence);
determining the first word includes an error if at least one of the syndromes is not equal to zero (paragraphs 22 and 48); and
reconstructing, in response to determining that the first word includes the error, the first word with a second level ECC circuit (Fig. 4, 418; the second level ECC is DECTED while the first level ECC is SECDED as disclosed in paragraph 18. In the case where a double bit error occurs and is detected by the first level ECC, it would have been obvious to employ the DECTED second level ECC to correct the error since that is the intended purpose of the second level ECC) by applying an error correction scheme (paragraph 42; DECTED ECC scheme) to the first word (Fig. 4, 412), the first level check bits (Fig. 4, 442), and second level check bits (Fig. 4, 444) to the second level ECC circuit (Fig. 1, 118).
Not explicitly disclosed is segments of a first word, and generating a respective group of syndromes for the segments. However, Pawlowski in an analogous art teaches segments of a first word (Fig. 6, 256 column groups; col. 8, lines 63-67) with a respective group of syndromes for the segments (col. 8, line 67-col. 9, line 2).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to apply the teachings of Lu to the memory structure of Pawlowski. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have reduced power consumption as stated by Lu in paragraph 47.
As per claims 2, 7, 15: Lu further teaches: generating the second level check bits with the second level EEC circuit (Fig. 4, 446) based on an error correction scheme (end of paragraph 18) applied to the first word (Fig. 4, 412) and the first level check bits (Fig. 4, 414).
As per claims 3, 8, 16: Lu further teaches: the first level ECC performs an error detection scheme (paragraph 18; the first ECC scheme may be Double-bit Error Detection); and the second level ECC performs an error correction scheme (paragraph 18; the second ECC scheme may be Double-bit Error Correction).
As per claims 4, 9, 17:
Lu further teaches the method and system, wherein: the error detection scheme is a double-error detection (DED) (paragraph 18; the first ECC scheme may be Double-bit Error Detection); and the error correction scheme is a double-error correction (DEC) (paragraph 18; the second ECC scheme may be Double-bit Error Correction).
Claim(s) 5, 10-12 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Powlowski in view of Meltzer (US Pat. 4,466,099).
As per claims 5, 10, 18: Lu et al teach the method and system above. Not explicitly disclosed is wherein: the error detection scheme is a single-error detection (SED); and the error correction scheme is a single-error correction (SEC). However, Meltzer in an analogous art teaches both a single-error correction code and a single-error detection code (col. 6, lines 7-11).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use SED for the error detection scheme and SEC for the error correction scheme. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Lu states that the second ECC may provide a higher level of protection than the first ECC logic/scheme (paragraph 18), and using SED/SEC as taught by Meltzer would have accomplished that.
As per claims 11, 19: Lu further teaches the memory system and method above, wherein: the error correction scheme is a double-error correction (DEC) (paragraph 18). Not explicitly disclosed is the error detection scheme is a single-error detection (SED). However, Meltzer in an analogous art teaches both a single-error detection code (col. 6, lines 7-11).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a SED scheme for the first ECC of Lu. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Lu suggests using a lower level of ECC protection, and SED is lower than DEC.
Claim(s) 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Powlowski in view of Kim et al (US Pat. Pub. 2014/0149669; hereinafter referred to as Kim)
As per claims 12, 20: Lu et al teach the memory system of claim 6 and method of claim 14. Not explicitly disclosed is wherein the memory device is one of magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), resistive random access memory (RRAM), or phase-change random access memory (PRAM). However, Kim in an analogous art teaches using a MRAM for a cache (paragraph 135).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a MRAM in Lu. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have reduced power consumption (paragraph 135).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Powlowski in view of Moyer (US Pat. Pub. 2010/0251036).
As per claim 13: Lu et al teach the memory system of claim 6. Not explicitly disclosed is wherein the syndrome calculation circuit comprises exclusive OR (XOR) trees. However, Moyer in an analogous art teaches a syndrome calculation circuit comprising an exclusive OR (XOR) tree (Fig. 3, 52; paragraph 40).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use an XOR tree for syndrome calculation. This modification would have been obvious for one of ordinary skill in the art at the time of filing because an XOR tree could have been used for calculating the syndromes required by Lu as shown by Moyer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111