Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 22 and 31
b. Pending: 1-7 and 22-34
Claims 1-7 are elected without traverse. Claims 8-21 have been canceled and claims 22-34 have been newly added.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
Applicant’s election without traverse of claims 1-7 in the reply filed on 6/3/2026 is acknowledged.
Information Disclosure Statement
No IDS has been submitted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 22-23, 26-27, 29 and 31-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 20250370715).
Regarding independent claim 1, Wu discloses an apparatus (Figs. 1-8) comprising:
bitlines overlying and coupled to vertical strings of memory cells for summing output currents from the memory cells during multiplication (Fig. 1 shows vertical bitlines BL coupled to memory array 11 and [0019] describes that a multiplication accumulation (MAC) operation is performed by the memory array 11 by inputting the input signals to the word lines WL0 to WLN−1 and analyzing the level of the currents flowing on the bit lines BL0 to BLM−1. Fig. 7A and [0049] describes that a plurality of accumulators 4023 are respectively coupled to the configurable adders 4022 and configured to accumulate the second sum signals of different input values to generate a plurality of output sum signals Out0 to OutM−1); and
a shunting network coupled to the bitlines (Figs. 1 and 7A show readout circuit 402a).
Regarding claim 2, Wu discloses all the elements of claim 1 as above and further wordlines arranged to run in an orthogonal direction to the bitlines (Fig. 1 shows wordlines WL run perpendicular to bitlines BL), the wordlines configured to apply a bias to gates of the memory cells during the multiplication (Fig. 1 and [0020] describes that control circuit 10 includes an input circuit 101 and a readout circuit 102. The input circuit 101 is configured to receive a plurality of input signals In0 to InN−1 respectively driving the word lines WL0 to WLN−1 of the memory array 11; select at least one first word lines respectively driven by at least one first input signals having a first input value; and provide an activating voltage to the at least one first word lines to activate the at least one first word lines in a first period).
Regarding claim 3, Wu discloses all the elements of claim 1 as above and further the shunting network comprises shunts that electrically connect two or more bitlines (Figs. 1, 7A show readout circuit 102 and 402a connects multiple bitlines).
Regarding claim 6, Wu discloses all the elements of claim 1 as above and further the shunting network comprises one or more conductive layers (Fig. 7A shows conductive lines running between layers of ADC 4021, multipliers 4022 and accumulators 4023).
Independent claim 22 and dependent claim 23 recite same claim limitations as recited by independent claim 1 and henceforth rejected the same way by Wu.
Regarding claim 26, Wu discloses all the elements of claim 22 as above and further the memory cells are configured as one or more strings of series-connected memory cells ([0018] describes NOR and NAND gate flash memories are applicable to implement memory elements of the memory cell. Memory arrays are arranged as series connected elements of strings).
Regarding claim 27, Wu discloses all the elements of claim 22 as above and further the shunting network comprises shunts that electrically connect two or more of the access lines (Figs. 1, 7A show readout circuit 102 and 402a connects multiple bitlines).
Regarding claim 29, Wu discloses all the elements of claim 22 as above and further the shunting network comprises one or more conductive layers (Fig. 7A shows conductive lines running between layers of ADC 4021, multipliers 4022 and accumulators 4023).
Independent claim 31 recites same claim limitations as recited by independent claim 1 and henceforth rejected the same way by Wu.
Regarding claim 32, Wu discloses all the elements of claim 31 as above and further the currents are summed from the memory cells during multiplication ([0019] describes that a multiplication accumulation (MAC) operation is performed by the memory array 11 by inputting the input signals to the word lines WL0 to WLN−1 and analyzing the level of the currents flowing on the bit lines BL0 to BLM−1. Fig. 7A and [0049] describes that a plurality of accumulators 4023 are respectively coupled to the configurable adders 4022 and configured to accumulate the second sum signals of different input values to generate a plurality of output sum signals Out0 to OutM−1).
Regarding claim 33, Wu discloses all the elements of claim 31 as above and further accumulation circuitry (Fig. 7A and [0049] describes plurality of accumulators 4023), wherein the shunting network (402a; Fig. 7A) comprises a digit line coupled to the accumulation circuitry (Fig. 7A shows bitlines BL and connected to accumulators 4023. Memory array 11 comprises of worldlines WL, which are electrically coupled to accumulators 4023).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 24-25, 28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20250370715) in view of Tanzawa (US 20130146980).
Regarding claim 4, Wu discloses all the elements of claim 1 as above and through Tanzawa further the bitlines are formed of a first material and the shunting network is formed of a second material different from the first material ([0074] describes shunts are formed of second conductive material different than bitlines. The interconnections can be formed of the third conductive material (e.g., metal, alloy)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanzawa to Wu in order to provide with apparatuses and methods for transposing select gates that reduce capacitive coupling, and thereby reduce noise and improve memory device operation as taught by Tanzawa ([0004]).
Regarding claim 5, Wu discloses all the elements of claim 1 as above and through Tanzawa further a conductive layer patterned to form the shunting network has a lower resistivity than a conductive layer patterned to form the bitlines ([0034] describes that second conductive material serving to shunt the first conductive material in order to decrease resistance along the select gate).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanzawa to Wu in order to provide with apparatuses and methods for transposing select gates that reduce capacitive coupling, and thereby reduce noise and improve memory device operation as taught by Tanzawa ([0004]).
Regarding claim 24, Wu discloses all the elements of claim 22 as above and through Tanzawa further the memory cells are configured in a vertical pillar (Fig. 1A and [0025] describes a pillar of semiconductor material for a string of memory cells).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanzawa to Wu in order to provide with apparatuses and methods for transposing select gates that reduce capacitive coupling, and thereby reduce noise and improve memory device operation as taught by Tanzawa ([0004]).
Regarding claim 25, Wu discloses all the elements of claim 22 as above and through Tanzawa further the shunting network is coupled to the access lines to reduce an effective resistance of the access lines ([0034] describes that second conductive material serving to shunt the first conductive material in order to decrease resistance along the select gate).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanzawa to Wu in order to provide with apparatuses and methods for transposing select gates that reduce capacitive coupling, and thereby reduce noise and improve memory device operation as taught by Tanzawa ([0004]).
Regarding claim 28, Wu discloses all the elements of claim 22 as above and through Tanzawa further a conductive layer patterned to form the shunting network has a lower resistivity than a conductive layer patterned to form the access lines ([0034] describes that second conductive material serving to shunt the first conductive material in order to decrease resistance along the select gate).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanzawa to Wu in order to provide with apparatuses and methods for transposing select gates that reduce capacitive coupling, and thereby reduce noise and improve memory device operation as taught by Tanzawa ([0004]).
Regarding claim 30, Wu discloses all the elements of claim 22 as above and through Tanzawa further the access lines are formed of a first material and the shunting network is formed of a second material different from the first material ([0074] describes shunts are formed of second conductive material different than bitlines. The interconnections can be formed of the third conductive material (e.g., metal, alloy)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanzawa to Wu in order to provide with apparatuses and methods for transposing select gates that reduce capacitive coupling, and thereby reduce noise and improve memory device operation as taught by Tanzawa ([0004]).
Claims 7 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20250370715) in view of Sakai et al. (US 20250391453).
Regarding claim 7, Wu discloses all the elements of claim 1 as above and through Sakai further a driver (Fig. 1 and [0102] shows bit line driver 107); and
an isolation transistor (Fig. 1 and [0117] describes column switch 118 is provided for every bit line BL. At this time, the column switch 118 can connect a selected bit line to the readout circuit 109 and disconnect a non-selected bit line from the readout circuit 109);
wherein the shunting network comprises a first digit line coupled to the driver and accumulation circuitry (Fig. 1 shows wordline WL electrically coupled to driver 107 and readout circuit 109);
wherein the isolation transistor is configured to isolate the accumulation circuitry from the first digit line and the driver (Fig. 1 and [0117] describes column switch 118 is provided for every bit line BL. At this time, the column switch 118 can connect a selected bit line to the readout circuit 109 and disconnect a non-selected bit line from the readout circuit 109).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Sakai to Wu in order to provide with memory cell array that perform multiplication and accumulation (MAC) on the basis of an input of the neural network and the weight as taught by Sakai ([0029]).
Regarding claim 34, Wu discloses all the elements of claim 31 as above and through Sakai further an isolation transistor, wherein the isolation transistor is configured to isolate accumulation circuitry from the shunting network (Fig. 1 and [0117] describes column switch 118 is provided for every bit line BL. At this time, the column switch 118 can connect a selected bit line to the readout circuit 109 and disconnect a non-selected bit line from the readout circuit 109).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Sakai to Wu in order to provide with memory cell array that perform multiplication and accumulation (MAC) on the basis of an input of the neural network and the weight as taught by Sakai ([0029]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 6/26/2026
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