DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-13, and 18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0306296 A1 (Furutani) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Furutani discloses, referring primarily to figures 1-4, a wiring substrate (2), comprising: a core substrate (3) comprising a glass substrate (4) and a through-hole conductor (8) penetrating through the glass substrate; a resin insulating layer (80) formed on the core substrate and having an opening (26F) extending through the resin insulating layer; a conductor layer (30F) formed on a surface of the resin insulating layer and comprising a seed layer (30Fa) formed by sputtering and an electrolytic plating layer (30Fb) formed on the seed layer; and a via conductor (40F) formed in the opening of the resin insulating layer such that the via conductor is configured to be electrically connected to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer, wherein the resin insulating layer includes resin (80) and inorganic particles (90) comprising first particles (91) and second particles (92) such that the first particles are partially embedded in the resin and that the second particles are embedded in the resin, and the resin insulating layer is formed such that the first particles have first portions (P) protruding from the resin and second portions embedded in the resin respectively and that the surface includes the resin and exposed surfaces of the first portions exposed from the resin (figure 3H) [claim 1], wherein the resin insulating layer is formed such that the inorganic particles include glass particles ([0028]) [claim 3], wherein the resin insulating layer is formed such that the inorganic particles include third particles having flat parts and that the flat parts of the third particles and the resin form an inner wall surface in the opening (figure 4) [claim 4], wherein the resin insulating layer is formed such that the flat parts of the third particles and the resin form substantially a common surface forming the inner wall surface in the opening (figure 4) [claim 5], wherein the resin insulating layer is formed such that each of the second particles has a spherical shape and that each of the third particles has a shape obtained by cutting the second particles with a plane (figure 4) [claim 6], wherein the resin insulating layer is formed such that the inorganic particles include oxygen ([0067]) [claim 7], wherein the conductor layer is formed such that the seed layer includes a first layer (31Fa) comprising an alloy ([0035]) and a second layer (31Fb) formed on the first layer and that the alloy in the first layer includes copper and aluminum ([0035]) [claim 8], wherein the conductor layer is formed such that the alloy in the first layer includes silicon ([0035]) [claim 9], wherein the conductor layer is formed such that the seed layer covering an inner wall surface in the opening of the resin insulating layer includes a first film and a second film and that a part of the first film is formed on the second film (figure 2) [claim 10], wherein the seed layer in the conductor layer is formed such that a leading end of the first film is formed on a trailing end of the second film (figure 1) [claim 11], wherein the seed layer in the conductor layer is formed such that the first film and the second film are formed in a same process ([0034]) [claim 12], wherein the seed layer in the conductor layer is formed such that the seed layer covering the inner wall surface in the opening of the resin insulating layer has a substantially step-shaped cross section ([0060]) [claim 13].
Similarly, Furutani discloses, a method of manufacturing a wiring substrate (2), comprising: forming a core substrate (3) comprising a glass substrate (4) and a through-hole conductor (8) penetrating through the glass substrate; forming a resin insulating layer (20F) on the core substrate such that the resin insulating layer has an opening (26F) extending through the resin insulating layer; forming a conductor layer (30F) on a surface of the resin insulating layer such that the conductor layer includes a seed layer (30Fa) formed by sputtering and an electrolytic plating layer (30Fb) formed on the seed layer; and forming a via conductor (40F) in the opening of the resin insulating layer such that the via conductor is configured to be electrically connected to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer, wherein the resin insulating layer includes resin (80) and inorganic particles (90) comprising first particles (91) and second particles (92) such that the first particles are partially embedded in the resin and that the second particles are embedded in the resin, and the resin insulating layer is formed such that the first particles have first portions (P) protruding from the resin and second portions embedded (figure 3H) in the resin respectively and that the surface includes the resin and exposed surfaces of the first portions exposed from the resin [claim 18], wherein the resin insulating layer is formed such that the inorganic particles include third particles having flat parts and that the flat parts of the third particles and the resin form an inner wall surface in the opening (figure 4) [claim 19], wherein the forming of the resin insulating layer includes forming the inorganic particles having protruding portions such that the protruding portions protrude from an inner wall surface in the opening of the resin insulating layer (figure 3H), and removing the protruding portions of the inorganic particles such that the third particles are formed ([0056]-[0059]) [claim 20].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 14-17 is/are rejected under 35 U.S.C. 103 as being obvious over Furutani.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 2, Furutani discloses the claimed invention as described above with respect to claim 1 except Furutani does not specifically state that the resin insulating layer is formed such that a ratio of a volume of the first portions to a volume of the first particles is greater than 0 and less than or equal to 0.4 [claim 2]. However, such a modification would merely amount to an optimization of the portion to be removed. Such optimization, a mere change in size, has been held to be within the skill of the ordinary artisan (MPEP 2144). Therefore, it would have been obvious, to one having ordinary skill in the art, to include the claimed features in the invention of Furutani. The motivation for doing so would have been to provide a smooth via wall surface.
Additionally, the modified invention of Furutani teaches, wherein the conductor layer is formed such that the seed layer includes a first layer comprising an alloy and a second layer formed on the first layer and that the alloy in the first layer includes copper and aluminum ([0035]) [claim 14], wherein the conductor layer is formed such that the alloy in the first layer includes silicon ([0035]) [claim 15], wherein the conductor layer is formed such that the seed layer covering an inner wall surface in the opening of the resin insulating layer includes a first film and a second film and that a part of the first film is formed on the second film (figure 1) [claim 16], wherein the seed layer in the conductor layer is formed such that a leading end of the first film is formed on a trailing end of the second film (figure 1) [claim 17].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JEREMY C. NORRIS
Examiner
Art Unit 2847
/JEREMY C NORRIS/Primary Examiner, Art Unit 2847
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