Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 4/14/2026. The remarks disclosed therein have been considered. Therefore, claims 1-33 remain pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 14, 17-18, 23-25, 30-31, 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park PG PUB 20140056069 (hereinafter Park).
Regarding independent claim 1, Park teaches an apparatus (figure 1) comprising:
memory cells arranged in a memory array (110 in figure 1); and
at least one controller (160 in figure 1) configured to: determine a respective context (“context” has been interpreted as any information used to decide how a cell is programmed, e.g., cell location, program order, neighboring cell state, verify condition, temperature) for each memory cell; program, based on the respective context, each memory cell to have an output current corresponding to a stored weight (“stored weight” can be threshold voltage, resistance, conductance, binary or multi-level state, thus under BRI, claim 1 of instant case covers: a memory array in which a controller programs cells differently depending on some per-cell information, such that the resulting cell state determines a read current. Park teaches to adjust programming based on conditions. Park teaches in figure 1 to divide cells into “near cell group” and “far cell group”, and teaches in figure 10 to use different verify voltages for “far-cell” and “near-cell”, in Park, stored weight = stored sate, output current = read current
Regarding claim 2, Park teaches the apparatus of claim 1, wherein the respective context is a location (“near cell group” and “far cell group in figure 1, [0009], “…reference distance from a word line voltage source in a word line direction…”, [0046], “…reference distance from the address decoder… the terms "near" and "far" are relative terms that may be understood in the context of the reference distance…”) in the memory array, and the programming compensates for IR drop based on the location of the memory cell (the term “ based on location” merely states the intended basis for compensation and does not impose a specific structure or operational limitation beyond what is already inherent in Park’s location-dependent programming).
Regarding claim 3, Park teaches the apparatus of claim 1, wherein the context is a location and a set of conditions during inference (e.g., read operations) on the memory array (Park teaches determining both memory cell location and operation conditions under which the memory array is accessed and read).
Regarding claim 4, Park teaches the apparatus of claim 2, wherein the IR drop corresponds to a voltage drop caused by current flowing through a resistance of a string of memory cells, and wherein the string includes the memory cell being programmed (Park teaches voltage drops caused by current flowing through resistive paths associated with multiple memory cells connected along conductive lines during programming operations. Such resistive paths inherently include strings of memory cells including cells being programmed).
Regarding claim 5, Park teaches the apparatus of claim 2, wherein the IR drop corresponds to a voltage drop caused by current flowing through a resistance of a bitline used to access the memory cell being programmed (Park teaches voltage drops caused by resistance of bitlines during programming and accessing memory cells, which inherently corresponds to IR drop along bitline used for access the memory cell being programmed).
Regarding claim 6, Park teaches the apparatus of claim 2, wherein the IR drop corresponds to a voltage drop caused by current flowing through a resistance of a network of bitlines and shunting lines (“shunting lines” has been interpreted as auxiliary conductive paths used to distribute or equalize current or voltages. Park teaches memory array conductive networks including bitlines and auxiliary conductive paths through which current flows during programming, resulting in voltage drops due to resistance).
Regarding claim 7, Park teaches the apparatus of claim 1, wherein the programming comprises applying one or more voltage pulses to the memory cell (figure 10 of Park teaches an ISPP program method).
Regarding claim 8, Park teaches the apparatus of claim 1, wherein after programming the memory cell, the output current is provided from the memory cell when a fixed bias is applied to a gate of the memory cell (Park teaches reading programmed cells by applying a fix read bias to gate of selected cell).
Regarding claim 9, Park teaches the apparatus of claim 1, wherein the respective context is a physical location or an address of the memory cell in the memory array (“near cell group” and “far cell group in figure 1, [0009], “…reference distance from a word line voltage source in a word line direction…”, [0046], “…reference distance from the address decoder… the terms "near" and "far" are relative terms that may be understood in the context of the reference distance…”)
Regarding claim 14, Park teaches the apparatus of claim 1, wherein a threshold voltage of the memory cell is adjusted during programming based on the respective context (Park teaches a program method).
Regarding claim 17, Park teaches the apparatus of claim 1, further comprising: bitlines overlying and coupled to vertical strings of the memory cells (figures 14, 17); and a shunting network coupled to the bitlines (“shunting network” has been interpreted as auxiliary conductive paths used to distribute or equalize current or voltages. Park teaches memory array conductive networks including bitlines and auxiliary conductive paths through which current flows during programming, resulting in voltage drops due to resistance).
Regarding claim 18, Park teaches the apparatus of claim 1, further comprising: interconnect (vias, contacts in figures 13-15 electrically connect access lines to higher level metal routing); access lines (wordlines in figure 1), wherein the memory cells are arranged in a plurality of sub-arrays (figure 12 shows BLK1 to BLKz), and the memory cells are accessed using the access lines (wordlines in figure 1); and metal lines (higher level metal routing, e.g., M1-M4) running in at least one plane above the access lines (wordlines in figure 1), wherein the metal lines are electrically coupled to the access lines by the interconnect.
Regarding independent claim 23, Park teaches an apparatus (figure 1) comprising: a memory array (110 in figure 1); and at least one controller (160 in figure 1) configured to: sequentially enable portions of the memory array to perform a multiplication (Park teaches enabling subsets of bitlines/columns rather than the entire array simultaneously, and further teaches activating different subsets at different times in order to control current magnitude and reduce IR drop, Park teaches that when a voltage is applied to cells, bitline currents are generated based on the stored cell states and that such currents are routed and accumulated via shunting structures. Under BRI, generating a current proportional to a stored weight in response to an applied input voltage constitutes a multiplication operation).
Regarding claim 24, Park teaches the apparatus of claim 23, wherein a first portion (111 in figure 1) of the memory array is enabled to provide a first accumulation result (Park teaches enabling a subset of cells such that currents from enabled cells are routed through shunting structures and combined to form partial accumulated current corresponding to that subset), a second portion (112 in figure 1) is enabled to provide a second accumulation result (Park teaches enabling a different subset of cells such that currents from enabled cells are routed through shunting structures and combined to form partial accumulated current corresponding to that subset), and the controller is configured to combine the first and second accumulation results (Park teaches routing accumulated currents from multiple subsets through shared shunting paths).
Regarding claim 25, Park teaches the apparatus of claim 23, wherein the controller is configured to select a number of portions to enable in sequence based on a context of the memory array ([0048], “…those skilled in the art will recognize that inventive concept is not limited to this particular configuration. The memory cell array 110 may be logically divided into three (3) or more memory cell groupings using two (2) or more reference distances…”, context here is interpreted as location)
Regarding independent claim 30, Park teaches an apparatus (figure 1) comprising: a shunting network (“shunting network” has been interpreted as auxiliary conductive paths used to distribute or equalize current or voltages. Park teaches memory array conductive networks including bitlines and auxiliary conductive paths through which current flows during programming, resulting in voltage drops due to resistance); and a memory array (figure 17) including dummy portions ([0206], “…Cell transistors between cell transistors used as string and ground selection transistors may be used as memory cells and dummy memory cells…”) used to provide openings in the memory array for electrically connecting bitlines (BL1-BL2 in figure 17) of the memory array to the shunting network.
Regarding claim 31, Park teaches the apparatus of claim 30, further comprising vertical interconnect formed in the openings (figure 14).
Regarding claim 33, Park teaches the apparatus of claim 30, wherein the shunting network includes metal lines located below the memory array, and the openings are slots in which vias are located (figure 14).
Claims 1, 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Tomita PG PUB 20050286299 (hereinafter Tomita).
Regarding independent claim 1, Tomita teaches an apparatus (title) comprising: memory cells arranged in a memory array (10 in figure 1); and at least one controller (3 in figure 1) configured to: determine a respective context (“context” has been interpreted as information associated with neighboring memory cels that affects programming or verification of a selected memory cell) for each memory cell; program, based on the respective context, each memory cell to have an output current corresponding to a stored weight (Tomita teaches in figure 7 to use neighboring cell information during program-verify operations).
Regarding claim 10, Tomita teaches the apparatus of claim 1, wherein the respective context is at least one value of weights stored in other memory cells coupled to a same bitline as the memory cell being programmed (Tomita teaches in figure 7 to use neighboring cell information during program-verify operations).
Claims 1, 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Jung PG PUB 20120163092 (hereinafter Jung).
Regarding independent claim 1, Jung teaches an apparatus (title) comprising: memory cells arranged in a memory array (110 in figure 1); and at least one controller configured to: determine a respective context (temperature indicated in S210 in figure 2) for each memory cell; program, based on the respective context, each memory cell to have an output current corresponding to a stored weight (Jung teaches in figures 2 and 3 to adjust program operations (program voltages) based on temperature).
Regarding claim 11, Jung teaches the apparatus of claim 1, wherein the respective context is a temperature (Abstract, “…the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage….”)
Regarding claim 12, Jung teaches the apparatus of claim 1, wherein a programming voltage is adjusted based on the respective context (figure 3A, 3B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung PG PUB 20120163092 (hereinafter Jung).
Regarding claim 13, Jung teaches the apparatus of claim 12, wherein adjustments are stored in a lookup table, and the programming voltage is determined using an adjustment selected from the lookup table (it would have been obvious to implement Jung’s temperature-dependent programming adjustment using a lookup table, as lookup table are a well-known and predictable design choice for storing pre-characterized operating parameters indexed by temperature in memory control circuit, in order to improve programmability).
Claim 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park PG PUB 20140056069 (hereinafter Park), in view of Mizutani PG PUB 20240111440 (hereinafter Mizutani).
Regarding claim 19, Park teaches the apparatus of claim 1, but does not teach apparatus further comprising: bitlines configured on a first wafer, wherein the bitlines are coupled to the memory cells; and a shunting network configured on a second wafer that is bonded to the first wafer, the shunting network electrically coupled to the bitlines.
Park teaches a memory device including memory cells in a memory array. Bitlines couples to the memory cells, metal interconnect structures located above or below the memory array and electrically couples to the bitlines (see figures 14, 15 of Park), Park teaches shunting network (“shunting lines” has been interpreted as auxiliary conductive paths used to distribute or equalize current or voltages) located beneath the memory array for reducing IR drop and distributing current. Park teaches memory array conductive networks including bitlines and auxiliary conductive paths through which current flows during programming, resulting in voltage drops due to resistance.
Mizutani teaches a multi-wafer/stacked semiconductor structure in which a first wafer includes memory cell circuitry and bitlines, a second wafer include support circuitry and metal interconnect networks, and wherein the second wafer is bonded to the first wafer using wafer bonding techniques, and electrical coupling between wafers is achieved via vertical interconnects. The advantage of doing so is to improve interconnect density, shorter interconnect length, and heterogeneous process optimization.
Park and Mizutani are analogous art because they address the same field of endeavor: memory storage apparatuses control circuit designs and control methods therefor. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Park and Mizutani before him, to modify the device structure of Park to integrate periphery circuitry on the second wafer taught by Mizutani, such that Park’s shunting network on a second wafer bonded to the memory cell wafer in order to improve routing density, reduce IR drop.
Regarding claim 20, the combination of Park and Mizutani teaches the apparatus of claim 19, wherein the second wafer (211 in figure 14 of Mizutani) is bonded to the first wafer (201 in figure 14 of Mizutani) using hybrid bonding ([0161] of Mizutani, “…control die 211 also includes a plurality of bond pads 1422 that line up with bond pads 1420 in order to bond control die 211 to control die 201…”)
Regarding claim 21, the combination of Park and Mizutani teaches the apparatus of claim 19, wherein the second wafer comprises accumulation circuitry coupled to the shunting network and configured to accumulate output currents from the memory cells during multiplication (Park teaches current summation/aggregation through shunting lines connected to multiple bitlines to support collective current behavior during memory operations. Mizutani teaches placing analog or accumulation circuitry on the bonded logic wafer).
Regarding claim 22, the combination of Park and Mizutani teaches the apparatus of claim 1, further comprising: bitlines coupled to the memory cells; and a shunting network coupled to the bitlines and located under the memory array (Park teaches current summation/aggregation through shunting lines connected to multiple bitlines to support collective current behavior during memory operations).
Allowable Subject Matter
Claims 15, 16, 26-29, 32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Park PG PUB 20140056069 (hereinafter Park).
Park discloses a nonvolatile memory device includes; a memory cell array designating a first memory cell group including first memory cells connected with a word line and disposed less than a reference distance from a word line voltage source in a word line direction, and a second memory cell group including second memory cells connected to the word line and disposed more than the reference distance from the word line voltage source in the word line direction, and control logic configured during a data processing operation to provide a first word line voltage to a first target memory cell among the first memory cells, and a second word line voltage different from the first word line voltage to a second target memory cell among the second memory cells.
Regarding claim 15, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: determining the respective context comprises determining an expected voltage drop based on at least one of an expected set of weights to be stored in the memory array during inference, or an expected input pattern to the memory array during inference.
Regarding claim 16, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: determining the respective context of each memory cell is based at least in part on at least one characteristic of one or more other memory cells programmed prior to the memory cell.
Regarding claim 26 (and its associated dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the context is an expected magnitude of current.
Regarding claim 28, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the context is based on values of at least one weight stored in memory cells to be used in the multiplication.
Regarding claim 29, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the controller is configured to select a number of portions to enable in sequence based on an expected voltage to be applied to at least one memory cell used in the multiplication.
Regarding claim 32, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: area provided by layout space of dummy bitlines is used to widen active bitlines to reduce IR drop, and each dummy bitline is next to an active bitline.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argument (claim 1):
“Park merely programs and reads cells to store and recover digital program data states using threshold-voltage distributions, not to produce a current value that corresponds to a “weight.””
Response:
Applicant’s argument is not persuasive.
The claim does not limit the term “stored weight” to a neural-network weight or to an analog quantity. Under the broadest reasonable interpretation (BRI) consistent with the specification, a “weight” encompasses any stored value represented by a memory cell, including a threshold voltage level, resistance state, or multi-bit programming state.
Park explicitly discloses programming memory cells to different threshold voltage levels representing stored information (e.g., [0047], [0060]-[0062]). Such stored threshold voltage levels constitute stored values and reasonably read on the claimed “stored weight”.
Applicant argument (claim 1):
“Park stores bits/multi-bit states, and not weights”.
Response:
This argument improperly attempts to narrow the claims.
The claim does not exclude digital representations. A stored bit or multi-bit state is a stored value, and under BRI, such stored values correspond to “stored weight”. Nothing in the claim requires a particular interpretation limited to machine-learning weights.
Applicant argument (claim 1):
“Park is directed to setting/verifying threshold-voltage distributions… not to programming each cell to achieve a particular output current value.”
Response:
This argument is not consistent with the scope of claim.
The claim does not require that a target current value be explicitly selected or targeted during programming. Rather, the claim requires that each memory cell be programmed such that an output current corresponds to the stored weight.
Park discloses that during a read operation, a bias is applied and a cell current is generated that depends on the programmed threshold voltages ([0051], [0094] of Park). Accordingly, the output current is a direct function of the stored threshold voltage (stored value), and therefore corresponds to the stored weight.
Applicant argument (claim 1):
“This is conventional memory-state sensing, and not identically describing outputting a current that corresponds to a stored “weight.””
Response:
Applicant’s argument is not persuasive.
The claim does not require any particular use of the current. Even if the current is used for sensing, the current produced during read operation is inherently dependent on the stored threshold voltage and therefore corresponds to the stored value (“weight”).
Applicant argument (claim 1):
“Park fails to disclose … programming each memory cell to have an output current corresponding to a stored weight”.
Response:
This conclusion is not supported.
As explained above, Park discloses programming memory cells to threshold voltage levels and reading those cells by generating a current dependent on the stored threshold voltage. Therefore, Park teaches programing each cell such that its output current corresponds to its stored value.
Applicant argument (claim 23):
“Park’s data processing operations are conventional memory operations (program verification/read), and not multiplication”.
Response:
The claim does not limit “multiplication” to a specific arithmetic or digital implementation.
Under BRI, generating a current that depends on both an applied voltage and a stored value constitutes a multiplication operation. Park discloses applying voltages to memory cells and generating currents dependent on stored threshold voltages (Park [0094], [0105]). Such operations reasonably read on multiplication.
Applicant argument (claim 23):
“Nothing in Park describes performing a multiplication (e.g., multiplying an input value by a stored weight to generate a product)”.
Response:
This argument imports limitations not recited in the claims.
The claim does not require an explicit arithmetic multiplication or a specific computational use. It only requires performing a multiplication operation, which under BRI included generating an output current dependent on an applied input and stored value.
Applicant argument (claim 23):
“Park’s portions (near/far groups) are defined for IR-drop/program-speed compensation, and not enabled sequentially to perform multiplication”.
Response:
Applicant’s argument is not persuasive.
Park discloses dividing memory cells into groups and performing program/verify/read operations under control logic ([0043]-[0046], figure 11). These operations are performed in cycles and loops, inherently involving sequential enabling of portions of the array.
Applicant argument (claim 23):
“ Park does not, for example, disclose any accumulation circuitry, partial results, or combining results from different enabled portions as part of a multiplication.”.
Response:
The claim does not require a particular form of accumulation circuitry or result combination. The cited disclosure of Park satisfies the claimed “multiplication” under BRI as discussed above.
Applicant argument (claim 30):
“ Park does not disclose a structure that a person of ordinary skill would understand as being a shunting network coupled to bitlines”.
Response:
Applicant’s argument is not persuasive.
Under BRI, a “shunting network” encompasses conductive structures that distribute or equalize current among memory cells or bitlines. Park discloses conductive paths including bitlines and common conductive paths through which current flows from multiple cells ([0193]-[0196], figure 13-17), which perform a current distribution function corresponding to a shunting network.
Applicant argument (Tomita):
“Tomita merely describes current being used for sensing to decide digital read data. For example, current is not targeted during programming as an output current corresponding to a stored weight.”
Response:
Applicant’s argument is not persuasive.
Tomita discloses applying read biases to generate a cell current dependent on stored state ([0008] of Tomita). Under BRI, such current corresponds to the stored value, regardless of whether the current is used for sensing.
Applicant argument (Jung):
“Jung merely determines a global operating condition (temperature). Jung does not identically teach a respective context for each memory cell for use in programming the particular memory cell.”
Response:
Applicant’s argument is not persuasive.
Jung teaches adjusting programming voltages based on detected conditions (e.g., temperature) affecting memory cells ([0034] of Jung). Under BRI, such conditions constitute context used in programming.
Applicant’s arguments rely on an unduly narrow interpretation of “stored weight”, “output current”, and “multiplication” that is not supported by the claim languish. Under BRI, the cited references teach or suggest all the claims limitations. According the rejections are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/ Primary Examiner, Art Unit 2824
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