Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/4/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 23-24 are rejected under 35 U.S.C. 102(a)2 as being anticipated by Wu PG PUB 20250370715 (hereinafter Wu).
Regarding independent claim 23, Wu teaches an apparatus comprising:
a memory array (11 in figures 1, 3A-3C, 4, 6A-6E); and
at least one controller (10 in figure 1, [0014], “…memory system 1 includes a control circuit 10 and a memory array 11…input circuit 10 is configured to receive input signals In0 to InN−1 to perform a multiplication accumulation operation with weight values stored in the memory array 11…”) configured to:
sequentially enable portions of the memory array to perform a multiplication ([0014], [0019], “…a multiplication accumulation (MAC) operation is performed by the memory array 11…”, Wu teaches divides activated word-line signals into groups and drives those signals in different periods, [0041], “…the input circuit 401 is configured to drive at most two word lines in each period …divide the first filter signals into a plurality of groups of second filter signals when a total number of the first driving signals is greater than a predetermined number…provide the plurality groups of second filter signals as driving signals to the corresponding word lines respectively in a plurality of second periods…”, [0048], “…the input circuit 401 is configured to dynamically adjust a total cycle count corresponding to each input value…”, figure 6A-6E teaches successive periods T1-T5 in which different groups of word lines are activated. Accordingly, the different groups constitute respective portions of the memory array that are enabled in sequence);
wherein the controller is configured to select a number of portions to enable in sequence based on a context of the memory array (Wu teaches the number of groups/portions is selected according to the number of word lines requiring activation relative to a predetermined permitted number. Wu teaches in [0035] that when a total number of active word lines exceeds a predetermined number, the input circuit will “dynamically adjusted cycle count of the multiple periods”, teaches in [0038]-[0040] to divide the selected input signals into multiple groups, and [0048] teaches determining a cycle count based on the required activations. Under BRI, the state of the memory array operation (i.e., the number of word lines/memory portions requiring activation for the particular MAC operation), is a context of the memory array).
Regarding claim 24, Wu teaches the apparatus of claim 23, wherein a first portion of the memory array is enabled to provide a first accumulation result, a second portion is enabled to provide a second accumulation result, and the controller is configured to combine the first and second accumulation results (Wu teaches in figure 7A ADC 4021, configurable multipliers 4022, and accumulators 4023 for generating accumulated output results. [0049] teaches that readout circuit receives output sum signals/MAC results. [0051] teaches that MAC results obtained during successive periods are accumulated, [0051], “…the accumulator is configured to accumulate all of the second sum signals calculated throughout the first to third periods T1-T5 to calculate output sum signal corresponding to the complete MAC result calculated using the weights and inputs...”, thus a first enabled group/portion generates a first partial sum, another enabled group/portion generates another partial sum, and the partial results are accumulated/combined to obtain the completed MAC result).
Allowable Subject Matter
Claims 1-22, 30-33 are allowed.
Claims 26-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Park PG PUB 20140056069 (hereinafter Park).
Park discloses a nonvolatile memory device includes; a memory cell array designating a first memory cell group including first memory cells connected with a word line and disposed less than a reference distance from a word line voltage source in a word line direction, and a second memory cell group including second memory cells connected to the word line and disposed more than the reference distance from the word line voltage source in the word line direction, and control logic configured during a data processing operation to provide a first word line voltage to a first target memory cell among the first memory cells, and a second word line voltage different from the first word line voltage to a second target memory cell among the second memory cells.
Regarding independent claim 1 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein determining the respective context comprises determining an expected voltage drop.
Regarding claim 26 (and its associated dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the context is an expected magnitude of current.
Regarding claim 28, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the context is based on values of at least one weight stored in memory cells to be used in the multiplication.
Regarding claim 29, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the controller is configured to select a number of portions to enable in sequence based on an expected voltage to be applied to at least one memory cell used in the multiplication.
Regarding independent claim 30 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: an area provided by layout space of dummy bitlines is used to widen active bitlines to reduce IR drop.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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