DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “first inner spacers spacing apart the first sidewalls of the first semiconductor layer from the gate structure; second inner spacers spacing apart the second sidewalls of the second semiconductor layer from the gate structure” of claim 11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities: the abbreviations “NFET” and “PFET” are recited in the claim without further description. Appropriate correction is required.
Claim 16 is objected to because of the following informalities: the abbreviations “NFET” and “PFET” are recited in the claim without further description. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11 recites the limitation “first inner spacers spacing apart the first sidewalls of the first semiconductor layer from the gate structure; second inner spacers spacing apart the second sidewalls of the second semiconductor layer from the gate structure”. The limitation was not described in the description as originally filed. The specification and drawings of the instant application describe inner spacers (214) separating NFET channel (204A) and p-type source/drain (218); inner spacers (220) separating PFET channel (206A) and n-type source/drain (224). See FIGS. 19B-19C and related text of the instant application. The instant application does not describe inner spaces separating semiconductor layer from gate structure.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 11-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are between a first direction and a vertical direction of claim 1 (“the NFET channel and the PFET channel being vertically spaced apart”); between a first direction and the top view of claim 1; between a second direction and the vertical direction of claim 1; between a second direction and the top view of claim 1.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are between a first direction and a stacking direction of claim (“a first semiconductor layer over a substrate; a second semiconductor layer over the first semiconductor layer”, and so on); between a second direction and the stacking direction of the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie (US 2023/0075966).
Regarding claim 1, Xie discloses, in FIG. 18 and in related text, a device comprising:
a gate structure (320) over a substrate (110);
n-type source/drain features (200) and p-type source/drain features (290) disposed around the gate structure, wherein from a top view, the gate structure has a quadrilateral profile, the n-type source/drain features (200) are respectively at opposite first and second sides of the quadrilateral profile of the gate structure (320) (see X cross section), and the p-type source/drain features (290) are respectively at opposite third and fourth sides of the quadrilateral profile of the gate structure (320) (see Y cross section);
an NFET channel (148) extending within the gate structure (320) and connecting the n-type source/drain features (200); and
a PFET channel (165) extending within the gate structure (320) and connecting the p-type source/drain features (290),
the NFET channel (148) and the PFET channel (165) being vertically spaced apart by the gate structure (320) from a first cross-sectional view (see X’ cross section) (see Xie, [0026], [0031], [0093], [0102]-[0103]: in FIG. 18, a p-type field effect transistor is placed on top of an n-type field effect transistor).
Regarding claim 9, Xie discloses the device of claim 1.
Xie discloses first isolation structures (120) under the n-type source/drain features (200) (see Xie, FIG. 18, [0033]
Regarding claim 10, Xie discloses the device of claim 9.
Xie discloses second isolation structures (270) under the p-type source/drain features (290) and spaced apart from the first isolation structures (120) (see Xie, FIG. 18, [0078]).
Claims 1, 5 and 8-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Schultz (US 2023/0096037).
Regarding claim 1, Schultz discloses, in FIGS. 1 and 5 and in related text, a device comprising:
a gate structure (102, 106 in FIG. 1; 308, 318, 502 in FIG. 5) over a substrate (302 in FIG. 5);
n-type source/drain features (104 outside gate structure 102 in FIG. 1; 306 outside gate structure 308 in FIG. 5) and p-type source/drain features (108 outside gate structure 106 in FIG. 1; 402 outside gate structure 502 in FIG. 5) disposed around the gate structure, wherein from a top view, the gate structure has a quadrilateral profile (overlapping region of 308 and 502 in FIG. 5), the n-type source/drain features are respectively at opposite first and second sides (front and back sides in FIG. 1) of the quadrilateral profile of the gate structure, and the p-type source/drain features are respectively at opposite third and fourth sides (left and right sides) of the quadrilateral profile of the gate structure;
an NFET channel (104 in FIG. 1) extending within the gate structure (102 in FIG. 1) and connecting the n-type source/drain features (104 outside gate structure 102 in FIG. 1); and
a PFET channel (108 in FIG. 1) extending within the gate structure (106 in FIG. 1) and connecting the p-type source/drain features (108 outside gate structure 106 in FIG. 1), the NFET channel (306 in FIG. 5) and the PFET channel (402 in FIG. 5) being vertically spaced apart by the gate structure (318) from a first cross-sectional view (see FIG. 5) (see Shultz, [0025]-[0026], [0033]-[0038]).
Regarding claim 5, Shultz discloses the device of claim 1.
Shultz discloses a Vdd contact (504) over one of the p-type source/drain features (402 outside gate structure 502 in FIG. 5); and
a Vss contact (320) over one of the n-type source/drain features (306 outside gate structure 308 in FIG. 5), wherein from a top view the Vdd contact and the Vss contact extend along different directions (horizontal and vertical directions in top view of FIG. 5) (see Shultz, [0033], [0036], [0038], [0047]: the device depicted in FIG. 5 is an inverter, which has p-type drain connected to Vdd and n-type drain connected to Vss, as depicted by the inverter P5/N5 in FIG. 11).
Regarding claim 8, Xie discloses the device of claim 1.
Xie discloses wherein the NFET channel (104: n-type doped silicon) is formed of a different material than the PFET channel (108: p-type doped silicon) (see Xie, [0025], [0031]).
Regarding claim 9, Xie discloses the device of claim 1.
Xie discloses first isolation structures (304) under the n-type source/drain features (314) (see Xie, FIG. 5, [0035]).
Regarding claim 10, Xie discloses the device of claim 9.
Xie discloses second isolation structures (316) under the p-type source/drain features (402 outside gate structure 502 in FIG. 5) and spaced apart from the first isolation structures (304) (see Xie, FIG. 5, [0036]).
Claims 16 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie (US 2023/0075966).
Regarding claim 16, Xie discloses, in FIG. 18 and in related text, a device comprising:
an NFET channel (148) over a substrate (110);
a PFET channel (165) at a different elevation than (above) the NFET channel;
a gate structure (320) shared by the NFET channel and the PFET channel;
n-type source/drain features (200) respectively on a first side and a second side of the NFET channel (148) (see X cross section); and
p-type source/drain features (290) respectively on a third side and a fourth side of the PFET channel (165) (see Y cross section), wherein the first side and the second side of the NFET channel are perpendicular to the third side and the fourth side of the PFET channel (see Xie, [0026], [0031], [0093], [0102]-[0103]: in FIG. 18, a p-type field effect transistor is placed on top of an n-type field effect transistor).
Regarding claim 20, Xie discloses the device of claim 16.
Xie discloses herein the NFET channel (148) and the PFET channel (165) have overlapping footprints on the substrate (110) (see Xie, FIG. 18, Y cross section).
Claims 16 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Schultz (US 2023/0096037).
Regarding claim 16, Schultz discloses, in FIGS. 1 and 5 and in related text, a device comprising:
an NFET channel (104) over a substrate (302);
a PFET channel (108) at a different elevation than the NFET channel;
a gate structure (102, 106) shared by the NFET channel and the PFET channel;
n-type source/drain features (104 outside gate structure 102) respectively on a first side and a second side (front and back sides) of the NFET channel (104); and
p-type source/drain features (108 outside gate structure 106) respectively on a third side and a fourth side (left and right sides) of the PFET channel (108), wherein the first side and the second side of the NFET channel are perpendicular to the third side and the fourth side of the PFET channel (see Shultz, [0025]-[0026], [0033]-[0038]).
Regarding claim 19, Shultz discloses the device of claim 16.
Shultz discloses the device is an inverter (see Shultz, [0025]).
Regarding claim 20, Shultz discloses the device of claim 16.
Shultz discloses wherein the NFET channel (306) and the PFET channel (402) have overlapping footprints on the substrate (302) (see Shultz, FIG. 5, [0033]-[0038]).
Allowable Subject Matter
Claims 2, 4, 6-7 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, Xie, discloses a first inner spacer; a second inner spacer. The prior art of records, individually or in combination, do not disclose nor teach “a first inner spacer separating the NFET channel from a first one of the p-type source/drain features; a second inner spacer separating the NFET channel from a second one of the p-type source/drain features” in combination with other limitations as recited in claim 2.
The prior art of record, Xie, discloses contacts electrically connecting one of the p-type source/drain features and one of the n-type source/drain features. The prior art of records, individually or in combination, do not disclose nor teach “a common source/drain contact electrically connecting one of the p-type source/drain features and one of the n-type source/drain features, the common source/drain contact having an L-shaped top view profile” in combination with other limitations as recited in claim 4.
The prior art of records, individually or in combination, do not disclose nor teach “wherein in the first cross-sectional view, the PFET channel has a greater length than the NFET channel” in combination with other limitations as recited in claim 6.
The prior art of records, individually or in combination, do not disclose nor teach “first inner spacers respectively on a third side and a fourth side of the NFET channel.” in combination with other limitations as recited in claim 17.
The prior art of records, individually or in combination, do not disclose nor teach “second inner spacers respectively on a first side and a second side of the PFET channel.” in combination with other limitations as recited in claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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