DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application is being examined under the pre-AIA first to invent provisions.
Drawings
2. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 230 in FIGS. 2A and 2B, and 227 in FIG. 2B.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
4. Claims 1-3, 8-12, 14-16, and 19-20 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Lee, et al (US 20100090286 A1), hereinafter Lee.
Regarding independent claim 1, Lee teaches a memory device (FIG. 1), comprising:
a stack of gates (FIG. 2B, 170a; ¶[0053]);
a semiconductor structure vertically extending through the stack of gates (¶[0046] teaches “ground select semiconductor structure 158 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0055] teaches “semiconductor structure 192 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0091] teaches “An upper portion of the semiconductor structure 192 may constitute a string select semiconductor structure 188.” Therefore, the elongated semiconductor pillar of FIG. 2B extending from source line 106 through the stack of gates to bit lines BL may be of the same semiconductor material.);
a charge storage structure horizontally interposed between the semiconductor structure and the stack of gates (FIG. 2B, 194; ¶[0055] teaches gate dielectric 194 may include a charge storage layer, with FIG. 2B showing 194 layered horizontally (in the First Direction) between 192 and 170a);
an additional semiconductor structure vertically offset from the stack of gates and in physical contact with the semiconductor structure (FIG. 2B, common source region 106, shown vertically offset from the stack of gates; ¶[0041]); and
a data line structure vertically offset (FIG. 2B, BL) from the stack of gates and coupled to the semiconductor structure (FIG. 2B, BL shown coupled to the elongated semiconductor pillar).
Regarding claim 2, Lee teaches the limitations of claim 1.
Lee further teaches the additional semiconductor structure physically contacts outer sidewalls of the semiconductor structure (FIG. 2B shows common source region 106 contacting the bottom sidewall of the elongated semiconductor pillar).
Regarding claim 3, Lee teaches the limitations of claim 1.
Lee further teaches the additional semiconductor structure comprises doped semiconductor material (¶[0041] teaches “common source region 106 doped with N-type impurities…”).
Regarding claim 8, Lee teaches the limitations of claim 1.
Lee further teaches a first select gate vertically interposed between the stack of gates and the data line structure (FIG. 2B, string select line structure 180; ¶[0059]); and
a second select gate vertically interposed between the stack of gates and the additional semiconductor structure (FIG. 2B, ground select structure 150; ¶[0045]).
Regarding claim 9, Lee teaches the limitations of claim 8.
Lee further teaches each of the first select gate and the second select gate is in physical contact with the charge storage structure (FIG. 2B shows string select line structure 180 contacting the “top” edge of charge storage layer 194, and ground select structure 150 contacting the “bottom” edge of charge storage layer 194).
Regarding independent claim 10, Lee teaches a memory device (FIG. 1), comprising:
gates vertically stacked relative to one another (FIG. 2B, 170a; ¶[0053]);
semiconductor material vertically extending continuously through the gates (¶[0046] teaches “ground select semiconductor structure 158 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0055] teaches “semiconductor structure 192 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0091] teaches “An upper portion of the semiconductor structure 192 may constitute a string select semiconductor structure 188.” Therefore, the elongated semiconductor pillar of FIG. 2B extending from source line 106 through the gates to bit lines BL may be of the same semiconductor material.);
a charge storage construct outwardly horizontally adjacent to the semiconductor material and vertically extending continuously through the gates (FIG. 2B, 194; ¶[0055] teaches gate dielectric 194 may include a charge storage layer, with FIG. 2B showing 194 layered horizontally (in the First Direction) between 192 and 170a, and 192 extending through the gates vertically (in the Third Direction));
doped semiconductor material vertically spaced from all of the gates and directly coupled to the semiconductor material (FIG. 2B, common source region 106, shown vertically spaced from the stack of gates and contacting the elongated semiconductor pillar; ¶[0041] teaches “common source region 106 doped with N-type impurities…”); and
a bit line (FIG. 2B, BL) coupled to the semiconductor material and vertically spaced from all of the gates and the doped semiconductor material (FIG. 2B, BL shown vertically spaced from gates 170a and common source region 106).
Regarding claim 11, Lee teaches the limitations of claim 10.
Lee further teaches dielectric material vertically interposed between pairs of the gates vertically neighboring one another (FIG. 2B, 170b; ¶[0053]), the dielectric material in physical contact with portions of the charge storage construct vertically interposed between the pairs of the gates (FIG. 2B, each layer of 170b shown contacting charge storage layer 194).
Regarding claim 12, Lee teaches the limitations of claim 10.
Lee further teaches the semiconductor material comprises polysilicon (¶[0046] teaches “ground select semiconductor structure 158 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0055] teaches “semiconductor structure 192 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0091] teaches “An upper portion of the semiconductor structure 192 may constitute a string select semiconductor structure 188.” Therefore, the elongated semiconductor pillar of FIG. 2B extending from source line 106 to bit lines BL may be of the same polysilicon material.).
Regarding claim 14, Lee teaches the limitations of claim 10.
Lee further teaches a side surface of the doped semiconductor material directly physically contacts a sidewall of the semiconductor material (FIG. 2B shows top side surface of common source region 106 contacting the bottom sidewall of the elongated semiconductor pillar).
Regarding claim 15, Lee teaches the limitations of claim 10.
Lee further teaches select gates vertically spaced from all of the gates (FIG. 2B, string select line structure 180; ¶[0059]; ground select structure 150; ¶[0045]; FIG. 2B shows select structures vertically spaced from all gates) and respectively substantially horizontally surrounding the semiconductor material (FIG. 2B shows 180 and 150 each substantially horizontally surround the elongated semiconductor pillar).
Regarding independent claim 16, Lee teaches a NAND memory device (FIG. 1; ¶[0020]), comprising:
a memory cell string (FIG. 1, 10; ¶[0038]) comprising:
an elongate structure comprising semiconductor material continuously vertically extending through a stack of gates (¶[0046] teaches “ground select semiconductor structure 158 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0055] teaches “semiconductor structure 192 may be formed of a single crystal or poly crystal semiconductor material”; ¶[0091] teaches “An upper portion of the semiconductor structure 192 may constitute a string select semiconductor structure 188.” Therefore, the elongated semiconductor pillar of FIG. 2B extending from source line 106 through the stack of gates to bit lines BL may be of the same semiconductor material.); and
a charge storage structure substantially horizontally surrounding the elongate structure and continuously vertically extending through the stack of gates (FIG. 2B, 194; ¶[0055] teaches gate dielectric 194 may include a charge storage layer, with FIG. 2B showing 194 layered on 192 horizontally (in the First Direction) and extending vertically (in the Third Direction));
a doped semiconductor structure in physical contact with a portion of the elongate structure of the memory cell string (FIG. 2B, common source line 106 is shown in contact with elongate semiconductor structure extending to bit line BL; ¶[0041] teaches “common source region 106 doped with N-type impurities…”); and
a data line structure (FIG. 2B, BL) coupled to the elongate structure of the memory cell string (FIG. 2B, BL shown coupled to the elongated semiconductor pillar).
Regarding claim 19, Lee teaches the limitations of claim 16.
Lee further teaches the stack of gates is vertically spaced from each of a drain select gate vertically positioned to proximate to the data line structure (FIG. 2B, string select line structure 180 is shown between the stack of gates 170a and bit line BL)) and a source select gate vertically positioned to proximate to the doped semiconductor structure (FIG. 2B, ground select structure 150 is shown between the stack of gates 170a and common source line 106).
Regarding claim 20, Lee teaches the limitations of claim 19.
Lee further teaches the elongate structure of the memory cell string continuously vertically extends through each of the drain select gate and the source select gate (the elongated semiconductor pillar of FIG. 2B is shown extending from source line 106 to bit lines BL through each of string select gate structure 150 and ground select gate structure 180.).
Claim Rejections - 35 USC § 103
5. The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 4 and 13 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lee, et al (US 20100090286 A1), hereinafter Lee, in view of Shim, et al (US 20100193861 A1), hereinafter Shim.
Regarding claim 4, Lee teaches the limitations of claim 3.
Lee does not teach the doped semiconductor material comprises n-type polysilicon.
Shim teaches the doped semiconductor material comprises n-type polysilicon (referencing FIGS. 4A-4E, ¶[0056] teaches “The common source line 106 may be a region doped with N-type impurities” and “the common source line 106 may include…doped polysilicon…”).
Regarding claim 13, Lee teaches the limitations of claim 12.
Lee does not teach the doped semiconductor material comprises doped polysilicon.
Shim teaches the doped semiconductor material comprises n-type polysilicon (referencing FIGS. 4A-4E, ¶[0056] teaches “The common source line 106 may be a region doped with N-type impurities” and “the common source line 106 may include…doped polysilicon…”).
Regarding claims 4 and 13, because both Lee and Shim teach a vertically stacked memory structure with an n-doped common source line formed above the substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the common source line of Shim with the common source line of Lee to yield predictable results. See MPEP § 2143(I)(B).
7. Claim 5 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lee, et al (US 20100090286 A1), hereinafter Lee, in view of Lee, et al (US 5748538 A), hereinafter Lee ‘538.
Regarding claim 5, Lee teaches the limitations of claim 1.
Lee does not teach the charge storage structure comprises a first nitride material, an oxide material, and a second nitride material.
Lee ‘538 teaches the charge storage structure comprises a first nitride material, an oxide material, and a second nitride material (FIG. 5; Col. 7, ll. 63-67 teach “a tunnel oxide layer 455, a floating gate 456 on the tunnel oxide layer 455, an insulating layer 457 formed by nitride-oxide-nitride and disposed on the floating gate 456, and a control gate 458 on the insulating layer 457”).
Because both Lee and Lee ‘538 teach a multi-layer gate dielectric structure having tunnel oxide/charge storage/insulating layers in a NAND flash, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the insulating layer of Lee ‘538 with the insulating layer of Lee to yield predictable results in a flash gate dielectric structure. See MPEP § 2143(I)(B).
8. Claims 6 and 18 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lee, et al (US 20100090286 A1), hereinafter Lee, in view of Lee, et al (US 20040047203 A1), hereinafter Lee ‘203.
Regarding claim 6, Lee teaches the limitations of claim 1.
Lee further teaches the charge storage structure comprises a tunnel dielectric material and a charge blocking material (referencing FIG. 3J, ¶[0088] teaches “gate dielectric 194 may have a multi-layered structure of a tunnel insulating layer/charge storage layer/blocking insulating layer”).
Lee does not teach the charge storage layer is a polysilicon material.
Lee ‘203 teaches a charge storage layer is a polysilicon material (FIG. 3d and ¶[0071] teach a poly-crystalline floating gate layer (112, FG) between tunneling oxide (108, TOX) and oxide-nitride-oxide (114, ONO) layers).
Regarding claim 18, Lee teaches the limitations of claim 16.
Lee further teaches the charge storage structure of the memory cell string comprises:
a tunnel dielectric material; and
a charge blocking material (referencing FIG. 3J, ¶[0088] teaches “gate dielectric 194 may have a multi-layered structure of a tunnel insulating layer/charge storage layer/blocking insulating layer”).
Lee does not teach the charge storage layer is one of a polysilicon material and an oxide material.
Lee ‘203 teaches the charge storage layer is one of a polysilicon material and an oxide material (FIG. 3d and ¶[0071] teach a poly-crystalline floating gate layer (112, FG) between tunneling oxide (108, TOX) and oxide-nitride-oxide (114, ONO) layers).
Regarding claims 6 and 18, because both Lee and Lee ‘203 teach a multi-layer gate dielectric structure having tunnel oxide/charge storage/insulating layers in a NAND flash, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the charge storage layer of Lee ‘203 with the charge storage layer of Lee to yield predictable results in a NAND flash gate dielectric structure. See MPEP § 2143(I)(B).
9. Claim 7 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lee, et al (US 20100090286 A1), hereinafter Lee, in view of Tang, et al (US 20110149656 A1), hereinafter Tang.
Regarding claim 7, Lee teaches the limitations of claim 1.
Lee does not teach a plug structure vertically interposed between and coupling the semiconductor structure and the data line structure.
Tang teaches a plug structure vertically interposed between and coupling the semiconductor structure and the data line structure (FIG. 2H; ¶[0039] teaches “contact plug 298 may be formed atop vertical TFT channel 255, and metal bitline 299 may be formed above contact plug 298”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Tang into the method of Lee to include bit line contact plugs. The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of operatively coupling bitlines to vertical channels (Tang ¶[0039]).
Allowable Subject Matter
10. Claims 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 17, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the doped semiconductor structure horizontally extends through the charge storage structure of the memory cell string to the semiconductor material of the elongate structure of the memory cell string.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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