DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 07/30/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 09/11/2025 & 01/08/2026. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 & 10-13 & 18-20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Yang et al (US20220165315).
Regarding claim 1, Yang discloses a memory circuit(FIG 1-3; 100), comprising: a memory array including a plurality of memory cells(120), wherein each of the plurality of memory cells is accessible through a plurality of access lines(WLs BLs);a delay circuit configured to receive a first clock pulse and delay the first clock pulse as a second clock pulse(FIG 1-3; [0045-0046] discloses 160 & 140, wherein comprising 162 , generating first clock pulse CKPB and second pulse CKPBd delayed of CKPB), wherein the second clock pulse immediately follows the first clock pulse (FIG 3; CKPBd followed immediately of CKPB);a logic gate configured to receive the first clock pulse and the second clock pulse(FIG 2; NAND1 gate receiving CKPB and CKPBd), and provide a pre-charge signal for pre-charging the plurality of access lines based on the first and second clock pulses; (FIG 2-3; NAND1 providing pre-charge signal BLEQB to memory access lines WLs and BLs based on CKPB and CKPBd) wherein the delay circuit includes a plurality of inverters and a plurality of transistors(FIG 2; INV1 INV2 and T1-T3), such that a time difference between a first transition edge of the first clock pulse and a second transition edge of the second clock pulse is extended in accordance with an increasing age of the memory circuit (FIG 3; time difference between CKPB and CKPBd clock edges time difference accordance with an increasing age of the memory circuit (note, there is always an increase of an age of the memory circuit as the circuit is being used e.g., reading or writing operation)).
Regarding claim 2, Yang discloses wherein the first clock pulse and the second clock pulse are within one clock cycle (FIG 3; CKPB and CKPd on one clock cycle e.g, D1 phase).
Regarding claim 3, Yang discloses wherein the first transition edge is a falling edge and the second transition edge is a rising edge (FIG 3; the clock falls of CKPB at start of D1 and the clock still rises of CKPBd at the start of D1).
Regarding claim 4 , Yang discloses wherein at least a first one of the memory cells is configured to be read during the first clock pulse(FIG 2-3; [0040] e.g, word line signal to WL2k is switched to high voltage, cell connected to WL2k is ready to be read), at least a second one of the memory cells is configured to be programmed(FIG 2-3; [0040] e.g, word line signal to WL2k is switched to high voltage, cell connected to WL2k is ready to be programmed), and the access lines of the memory cells are configured to be pre- charged to a logic state between the first clock pulse and the second clock pulse(FIG 3; access lines e.g., WL1 WL2k on pre-charge at logic high e.g., D1 phase).
Regarding claim 10, Yang discloses wherein the pre-charge signal has a pulse width determined based on the time difference (FIG 3; pre-charge signal BLEQB having pulse width determined based on the difference of CKPBd delayed of CKPB).
Regarding claim 11, Yang discloses wherein the delay circuit further includes a plurality of metal lines, each of which has a length proportional to a height of the memory array (FIG 1-2; 160 comprising 162 having plurality of metal lines length proportional to a height of the 120).
Regarding claim 12, Yang discloses wherein the delay circuit further includes a plurality of metal lines, each of which has a length proportional to a width of the memory array (FIG 1-2; 160 comprising 162 having plurality of metal lines length proportional to a width of the 120).
Regarding claim 13, Yang discloses a memory circuit(FIG 1; 100), comprising: a delay circuit configured to receive a first clock pulse and delay the first clock pulse as a second clock pulse(FIG 1-3; [0045-0046] discloses 160 & 140, wherein comprising 162 , generating first clock pulse CKPB and second pulse CKPBd delayed of CKPB), wherein the first clock pulse and the second clock pulse are within one clock cycle(FIG 3; CKPB and CKPd on one clock cycle e.g, D1 phase); wherein the delay circuit includes a plurality of inverters and a plurality of transistors(FIG 2; INV1 INV2 and T1-T3), and the plurality of transistors are configured such as to delay a rising edge of the second clock pulse that follows a falling edge of the first clock pulse in accordance with an increasing age of the memory circuit (FIG 3; time difference between CKPB and CKPBd clock edges time difference accordance with an increasing age of the memory circuit (note, there is always an increase of an age of the memory circuit as the circuit is being used e.g., reading or writing operation)).
Regarding claim 18, Yang discloses discloses further comprising:a logic gate configured to receive the first clock pulse and the second clock pulse(FIG 2-3; CKPB and CKPBd being receiving by logic gate), and provide a pre-charge signal by OR'ing the first clock pulse and the second clock pulse (BLEQB generated by OR CKPBd and CKPB);wherein the pre-charge signal is configured for pre-charging a plurality of bit lines (FIG 2; BLEQB signal for pre-charging BLs/BLB), and the pre-charge signal has a pulse width determined based on a time difference between the first clock pulse and the second clock pulse(FIG 3; time difference between the start of CKPB and CKPBd on BLEQB).
Regarding claim 19, Yang discloses a method, comprising: receiving a first clock pulse configured for a first operation of a first memory cell within a memory array(FIG 1; 100 comprising method for a read operation of BCs in 120).; delaying the first clock pulse as a second clock pulse configured for a second operation of a second memory cell within the memory array(FIG 1-3; [0045-0046] discloses 160 & 140, wherein comprising 162 , generating first clock pulse CKPB and second pulse CKPBd delayed of CKPB), wherein the first clock pulse and the second clock pulse, that immediately follows a falling edge of the first clock pulse(FIG 3; CKPBd followed immediately of CKPB), are within one clock cycle((FIG 3; CKPB and CKPd on one clock cycle e.g, D1 phase); pre-charging a first bit line coupled to the first memory cell and a second bit line coupled to the second memory cell(FIG 2-3; NAND1 providing pre-charge signal BLEQB to memory access lines WLs and BLs based on CKPB and CKPBd); and delaying a rising edge of the second clock pulse(FIG 3; CKPBd is delayed).
Regarding claim 20, Yang discloses further comprising: providing, between the first clock pulse and the second clock pulse, a pre-charge signal with a pulse width determined based on the falling edge of the first clock pulse and the rising edge of the second clock pulse; wherein the pre-charge signal is configured for pre-charging all bit lines of the memory array(FIG 2-3; providing pre-charge signal width BLEQB e.g., D1, based on the falling and rising edge of CKPB and CKPBd and pre-charging memory access lines BLs).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-8 & 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al in view of Yoon et al (US20220336004).
Regarding claim 5, Yang discloses wherein the plurality of transistors include p- type transistors (FIG 2; T1-T3 p-type transistors connected to plurality of inverters INV1 and INV2).
However, Yang does not disclose connected to even-numbered stages of the plurality of inverters, and wherein respective gate terminals of the p-type transistors are connected to VSS.
In the same field of endeavor, Yoon discloses connected to even-numbered stages of the plurality of inverters (FIG 8A; discloses UC13 UC14 comprising p-type transistors even 421 425 connected inverters), and wherein respective gate terminals of the p-type transistors are connected to VSS (421 and 425 gate connected to VSS).
Yang and Yoon are analogous art because they are all directed to a semiconductor memory device with a duty cycle with time, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Yang to include Yoon because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Yoon in the teachings of Yang for the benefits compensating the time delay and correcting the duty cycle error to enhance the performance of the semiconductor memory device [0004 & 0010 Yoon].
Regarding claim 6, Yang in view of Yoon disclose wherein the plurality of transistors(Yang FIG 2; T1-T3 p-type transistors connected to plurality of inverters INV1 and INV2) include p- type transistors connected to even-numbered stages of the plurality of inverters and type transistors connected to odd-numbered stages of the plurality of inverters(Yoon FIG 8A; discloses p-type transistors even 421 425 and 411 415 connected inverters) and wherein respective gate terminals of the p-type transistors are connected to VSS and respective gate terminals of the type transistors are connected to VDD( wherein respective gate terminals of the p-type transistors are connected to VSS (421 and 425 gate connected to VSS) and 411 415 connected to VDD).
However, the combinations of Yang in view of Yoon does not discloses n-type transistors.
However, the particular choice of types of transistors was held to be an obvious matter of design choice. Since Yoon discloses p-types transistors of odd and even that are connected to gate of Vss and Vdd as shown in FIG 8A, it would be obvious to change some of the transistors to n-types. Please see MPEP 2144.04.
Regarding claim 7, Yang In view of Yoon discloses wherein the plurality of transistors include a p- type transistor(Yang FIG T1-T3 p-type transistors connected to plurality of inverters INV1 and INV2) connected to a first stage of the plurality of inverters and an n-type transistor connected to an input of a second stage of the plurality of inverters(Yoon FIG 8A; UC11-UC14 wherein 412 416 p-type 413 417 and 413 417 n types), and wherein respective gate terminals of the p-type transistor and the n-type transistor are both connected to a control signal (gates of 412 416 and 413 417 connected to control signal e.g., CLK).
Regarding claim 8, Yang In view of Yoon disclose wherein the control signal is provided at a first logic state during the first clock pulse(Yoon FIG 9; CLK1 405), the time difference(start time of 405), and the second clock pulse(FIG 9; CLKQ 406), and the control signal is provided at a second logic state during other time period different from the first clock pulse, the time difference(FIG 9; 406 is delayed vs 405 e.g., time difference), or the second clock pulse.
Regarding claim 14, Yang discloses wherein the plurality of transistors include p- type transistors (FIG 2; T1-T3 p-type transistors connected to plurality of inverters INV1 and INV2).
However, Yang does not disclose connected to even-numbered stages of the plurality of inverters, and wherein respective gate terminals of the p-type transistors are connected to VSS.
In the same field of endeavor, Yoon discloses connected to even-numbered stages of the plurality of inverters (FIG 8A; discloses UC13 UC14 comprising p-type transistors even 421 425 connected inverters), and wherein respective gate terminals of the p-type transistors are connected to VSS (421 and 425 gate connected to VSS).
Yang and Yoon are analogous art because they are all directed to a semiconductor memory device with a duty cycle with time, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Yang to include Yoon because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Yoon in the teachings of Yang for the benefits compensating the time delay and correcting the duty cycle error to enhance the performance of the semiconductor memory device [0004 & 0010 Yoon].
Regarding claim 15, Yang in view of Yoon disclose wherein the plurality of transistors(Yang FIG 2; T1-T3 p-type transistors connected to plurality of inverters INV1 and INV2) include p- type transistors connected to even-numbered stages of the plurality of inverters and type transistors connected to odd-numbered stages of the plurality of inverters(Yoon FIG 8A; discloses p-type transistors even 421 425 and 411 415 connected inverters) and wherein respective gate terminals of the p-type transistors are connected to VSS and respective gate terminals of the type transistors are connected to VDD( wherein respective gate terminals of the p-type transistors are connected to VSS (421 and 425 gate connected to VSS) and 411 415 connected to VDD).
However, the combinations of Yang in view of Yoon does not discloses n-type transistors.
However, the particular choice of types of transistors was held to be an obvious matter of design choice. Since Yoon discloses p-types transistors of odd and even that are connected to gate of Vss and Vdd as shown in FIG 8A, it would be obvious to change some of the transistors to n-types. Please see MPEP 2144.04.
Regarding claim 16, Yang In view of Yoon discloses wherein the plurality of transistors include a p- type transistor(Yang FIG T1-T3 p-type transistors connected to plurality of inverters INV1 and INV2) connected to a first stage of the plurality of inverters and an n-type transistor connected to an input of a second stage of the plurality of inverters(Yoon FIG 8A; UC11-UC14 wherein 412 416 p-type 413 417 and 413 417 n types), and wherein respective gate terminals of the p-type transistor and the n-type transistor are both connected to a control signal (gates of 412 416 and 413 417 connected to control signal e.g., CLK).
Claim(s) 9 & 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al in view of Yoon et al further in view of Oyama et al (US20110292735).
Regarding claim 9, Yang In view of Yoon disclose wherein the plurality of transistors connected to an output of a last stage of the plurality of inverters (Yoon FIG 7 & 8A; plurality of transistors UC11-UC14 connected to an output of e.g., MCCKQ line fed into 450a (comprising plurality of inverters 451).
However, Yang in view of Yoon do not disclose include a transmission gate, and wherein the transmission gate has a p-type transistor with its gate terminal connected to VSS and an n- type transistor with its gate terminal connected to VDD.
In the same field of endeavor, Oyama discloses include a transmission gate, and wherein the transmission gate has a p-type transistor with its gate terminal connected to VSS and an n- type transistor with its gate terminal connected to VDD (FIG 7; [0054] discloses transmission gate 59 having p-type transistor connected to Vss and n-type transistor connected to Vdd (source)).
Yang in view of Yoon and Oyama are analogous art because they are all directed to a semiconductor memory device with accessing operation, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Yang in view of Yoon to include Oyama because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Oyama in the teachings of Yang in view of Yoon for the benefits avoiding a large current consumption during accessing operation that increases power consumption of the semiconductor memory device. [0006 Oyama].
Regarding claim 17, Yang In view of Yoon disclose wherein the plurality of transistors connected to an output of a last stage of the plurality of inverters (Yoon FIG 7 & 8A; plurality of transistors UC11-UC14 connected to an output of e.g., MCCKQ line fed into 450a (comprising plurality of inverters 451).
However, Yang in view of Yoon do not disclose include a transmission gate, and wherein the transmission gate has a p-type transistor with its gate terminal connected to VSS and an n- type transistor with its gate terminal connected to VDD.
In the same field of endeavor, Oyama discloses include a transmission gate, and wherein the transmission gate has a p-type transistor with its gate terminal connected to VSS and an n- type transistor with its gate terminal connected to VDD (FIG 7; [0054] discloses transmission gate 59 having p-type transistor connected to Vss and n-type transistor connected to Vdd (source)).
Yang in view of Yoon and Oyama are analogous art because they are all directed to a semiconductor memory device with accessing operation, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Yang in view of Yoon to include Oyama because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Oyama in the teachings of Yang in view of Yoon for the benefits avoiding a large current consumption during accessing operation that increases power consumption of the semiconductor memory device. [0006 Oyama].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Aizawa et al (US20150131392 FIG 2; [0209] discloses delay time caused by inverters, a time period to a time difference between the rise of read clock and fall of the word line signal and having pre-charge signal PC1).
Idei et al (US6128248 FIG 2; discloses clocks n1 n2, wherein n2 is delayed than n1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/ Primary Examiner, Art Unit 2827
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