Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 20 are pending.
Any references to applicant’s specification are made by way of applicant’s U.S. pre-grant printed patent publication.
This action is in response to the communication filed on 7/30/24.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features of a “trim circuit” and “a redundancy circuit” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 17, the subject matter of “a trim circuit” and “a redundancy circuit” are not adequately described within the applicant’s originally filed disclosure.
For example, regarding the term “redundancy circuit”, the applicant’s written description mentions this term only three times within the specification, and only briefly states that the purpose of the “redundancy circuit” is to “…to replace defective I/O's and wordlines…” (see Specification, par. 26).
However, neither the applicant’s drawings nor the specification ever describe the physical structure of the “redundancy circuit”. Furthermore, as to the intended purpose of the “redundancy circuit” (i.e. “…to replace defective I/O's and wordlines…”), the applicant’s written specification fails to ever disclose specifically how (i.e. the algorithm, formula, series of steps) that such functionality is to be accomplished. The examiner points out that simply restating the claimed function (or perhaps something similar “…to replace a defective portion of an interconnect routing…”) is not sufficient to satisfy the written description requirement (e.g. see MPEP 2161.01).
For example, regarding the term “trim circuit”, the examiner points out that the applicant’s written description appears only to describe the intended purpose or function of the trim circuit (e.g. to use trim information “…to adjust a reference current…” or “…to adjust temperature-dependent trim…”; e.g. see Specification, par. 22-24).
However, neither the applicant’s drawings nor the specification ever describe the physical structure of the “trim circuit”. Furthermore, as to the intended purpose of the “trim circuit” (i.e. “…to adjust …”), the applicant’s written specification fails to ever disclose specifically how (i.e. the algorithm, formula, series of steps) that such adjustments are to be accomplished. The examiner points out that simply restating the claimed function (or perhaps something similar “…to adjust an operational characteristic of a circuit…”) is not sufficient to satisfy the written description requirement (e.g. see MPEP 2161.01).
Regarding claim 8, the recited functions of “…adjusting an operational characteristic of a circuit based on trim information …” and “…replacing a defective portion of an interconnect routing based on redundancy information…” fail to be adequately described within the applicant’s originally filed disclosure.
The examiner notes that the functional claim limitations of computer implemented inventions are required to be described within the applicant’s written disclosure as to specifically how such functionality is achieved (e.g. How are defective portions of an interconnect replaced? How are adjustments to the operational characteristics implemented?). Thus, the algorithm or steps/procedure for accomplishing the claimed function must be describe in sufficient detail (i.e. simply restating the claimed function is not sufficient to satisfy the written description requirement). see MPEP 2161.01
Depending claims are rejected by virtue of dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (Wu), US 2021/0026603 A1 in view of Kim, US 2021/0184871 A1.
Regarding claim 1, Wu discloses:
An circuit (e.g. Wu, fig. 1; par. 15), comprising:
…
… a processor configured to perform a hashing function on a portion of … information to generate hashed bits (e.g. Wu, par. 4, 18, 22; claim 11);
Wu discloses an integrated circuit designed to extract bits of information stored with a memory device, such as information set within a OTP memory cell, e.g. a fuse, of the memory device (e.g. Wu, par. 18, claim 11) and use said extracted information to hash and create a random value (e.g. Wu, Abstract). Wu, however, does not appear to explicitly disclose the specific informational content of said stored information (e.g. “trim” or “redundancy” information) or the specific usage of said “trim” or “redundancy” information to perform other functions such as operational adjustments or replacements.
However, like Wu, Kim also discloses an integrated circuit designed to extract bits of information from a memory device, e.g. a fuse (e.g. Kim, fig. 2:910; par. 47, 48), so as to generate a random value (e.g. Kim, Abstract).
Furthermore, Kim teaches that the type of information stored within the fuse can be “trim” and “redundancy” information (e.g. Kim, par. 47-51), which are used by circuitry within the integrated circuit to perform the functions of replacing bad memory addresses with redundant addresses (e.g. Kim, par. 52; fig. 2:930, 920; i.e. a “redundancy circuit” to replace “defective interconnect routing”) and to select portions of bit line sense amplifiers during operation (e.g. Kim, par. 53, fig. 2:800; i.e. a “trim circuit” to adjust “operational characteristics”).
It would have been obvious to one of ordinary skill in the art to employ the informational content within fuses and the circuitry associated usage of such information (i.e. “trim”, “redundancy”) as taught by Park within the system of Wu. This would have been obvious because one of ordinary skill in the art would have been motivated by the teachings that the information stored within fuses of a circuit can include “trim” and “redundancy” information, usable by the circuitry of the device to also perform the functions of repairing the circuit and controlling its operation (e.g. Kim, par. 32, 42, 48).
Thus, the combination enables:
…a trim circuit (e.g. Kim, fig. 2:800) configured to adjust an operational characteristic of a circuit based on trim information comprising a tuning parameter of the adjusted operational characteristic (e.g. Kim, par. 48, 53);
a redundancy circuit (e.g. Kim, fig. 2:930, 920) configured to replace a defective portion of an interconnect routing based on redundancy information comprising an address mapping of the replaced defective portion (e.g. Kim, par. 48, 52; the address locations point to locations of bad memory cells – i.e. “address mapping”);
…
Regarding claim 2, the combination enables:
wherein the circuit comprises a sense amplifier, an analog-to-digital converter, a digital-to-analog converter, or a sensor (e.g. Kim, par. 53).
Regarding claim 3, the combination enables:
wherein the trim information comprises one or more of sense amplifier trim information, analog-to-digital converter trim information, digital-to-analog trim information, and sensor trim information (e.g. Kim, par. 48, 53) .
Regarding claim 4, the combination enables:
wherein the interconnect routing comprises an input/output line, a wordline, or a bitline (e.g. Kim, par. 48).
Regarding claim 5, the combination enables:
wherein the redundancy information comprises one or more of input/output circuit repair information, a physical address associated with a repaired wordline in a memory device, and a physical address associated with a repaired bitline in the memory device (e.g. Kim, par. 48).
Regarding claim 6, the combination enables:
wherein to perform the hashing function on the portion of the trim and redundancy information, the processor is further configured to perform a cryptographic hashing function on the portion of the trim and redundancy information to generate the hashed bits (e.g. Wu, par. 18, 25; Kim, par. 53 – information within the fuse is hashed).
Regarding claim 7, the combination enables:
wherein the processor is further configured to determine statistical properties of the hashed bits based on one or more of a Hamming weight analysis on the hashed bits, an inter-Hamming distance (HD) analysis on the hashed bits, an intra-HD analysis on the hashed bits, and an autocorrelation operation on the hashed bits (e.g. Wu, par. 14).
Regarding claim 8, the combination enables:
wherein the processor is further configured to, in response to the statistical properties of the hashed bits failing to meet one or more criteria, perform the hashing function on another portion of the trim and redundancy information to generate other hashed bits (e.g. Wu, par. 21, 29, 32 – number generation continues until a truly random number is generated).
Regarding claims 9, 10, and 12 – 20, they are method and system claims, essentially corresponding to the device claims above, and they are rejected, at least, for the same reasons.
Furthermore, regarding claim 10, the combination enables:
further comprising retrieving the trim and redundancy information to extract bits associated with the portion of the trim and redundancy information (e.g. Wu, par. 18; e.g. Kim, par. 53),
wherein the retrieving comprises: initializing a linear feedback shift register (LFSR) with a first subset of the trim and redundancy information (e.g. Wu, par. 21; fig. 3:142);
cycling the LFSR based on a value associated with a second subset of the trim and redundancy information, wherein the second subset is different from the first subset of the trim and redundancy information (e.g. Wu, fig. 3: cycling feedback using Bc, Sd, Pfb);
and outputting contents of the cycled LFSR to generate the extracted bits (e.g. Wu, par. 21; fig. 3:16).
Furthermore, regarding claim 17, the combination enables:
… a physical unclonable function (PUF) circuit configured to:… (e.g. Wu, par. 18; e.g. Kim, Abstract) …
…
… and in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits (e.g. Wu, par. 14, 21, 29, 32 – random number generation process continues until a “truly” random number is generated).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (Wu), US 2021/0026603 A1, in view of Kim, US 2021/0184871 A1, in view of Hou et al. (Hou), “A dynamically configurable LFSR-based PUF design against machine learning attacks”.
Regarding claim 11, Wu discloses a PUF design that appears to incorporate a single multiplexer circuit. Hou, however, also discloses a PUF design that incorporates a plurality of multiplexer circuits (e.g. Hou, Abstract; sect. 2.2; fig. 1). It would have been obvious to one of ordinary skill in the art to incorporate the usage of a plurality of multiplexer circuits as taught by Hou within the system of Wu. This would have been obvious because one of ordinary skill in the art would have been motivated by the teachings that the plurality of multiplexers comprises an advantage and increases the robustness of the PUF design (e.g. Hou, sect. 2.2; pg. 32, col. 1, par. 4).
Thus, the combination enables:
retrieving the trim and redundancy information to extract bits associated with the portion of the trim and redundancy information (e.g. Wu, par. 18; e.g. Kim, par. 53),
wherein the retrieving comprises: inputting a first subset of the trim and redundancy information into multiplexer circuits (e.g. Wu, par. 16, 17; Hou, fig. 1; sect. 2.2);
and selecting an output of each of the multiplexer circuits based on a second subset of the trim and redundancy information to generate the extracted bits, wherein a number of bits in the second subset is half of that in the first subset of the trim and redundancy information (e.g. Hou, fig. 1:arbiter; sect. 2.2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
See Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFERY L WILLIAMS whose telephone number is (571)272-7965. The examiner can normally be reached 7:30 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Farid Homayounmehr can be reached on 571-272-3739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEFFERY L WILLIAMS/Primary Examiner, Art Unit 2495