DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 30 July 2026 was filed after the mailing date of the Office Communication on 12 May 2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Office acknowledges receipt on 12 August 2026 of Applicants’ amendments in which claims 1, 11, 15, and 16 are amended. The Office withdraws the indefiniteness rejection applied to claim 15 in the Office Communication dated 12 May 2026 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1, 17, and 33 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
The indicated allowability of claims 5 and 18 is withdrawn in view of the newly discovered reference(s) to Cheng et al. (US20200044060A1), which was identified in Applicants’ IDS submitted 30 July 2026 by its German counterpart. Rejection(s) based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20190067452A1) in view of Cheng et al. (US20200044060A1).
Regarding claim 1, Cheng teaches a method, comprising:
depositing a plurality of alternating layers of first and second semiconductor layers (110, 112) on a substrate (102), wherein the substrate (102) comprises germanium {Figs. 1A-1, 1A-2, 4; [0019, 0023]};
forming a source/drain region (132B and/or 134) in contact with the plurality of first and second semiconductor layers (110, 112) {Figs. 1B-1, 1B-2, 4B; [0049]};
removing first semiconductor layers (112) to form a plurality of first openings between the plurality of second semiconductor layers (110) and a second opening between a bottom-most second semiconductor layer (110) and the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copies of Cheng’s Figs. 3E-1, 3E-2 below; second opening is between lowermost 110 and 102 along a diagonal line};
removing an upper portion of the substrate (102) through the second opening to form a third opening, wherein the bottom surface of the source/drain region (132B and/or 134) extends into the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copies of Cheng’s Figs. 3E-1, 3E-2 below};
forming a gate structure (162, 164) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}, comprising:
forming a first portion (portion of 162, 164 within first openings) of the gate structure (162, 164) within each of the first openings {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}; and
forming a second portion (portion of 162, 164 within third opening) of the gate structure (162, 164) within the third opening {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}.
Cheng does not necessarily teach the third opening extends below a bottom surface of the source/drain region.
In an analogous art, Cheng ‘060 teaches in Figs. 2A, and 30B and paragraphs [0105-0106] a third opening (59 filled by 106, 106 in Fig. 2A) extends below a bottom surface of the source/drain region (80). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng’s method based on the teachings of Cheng ‘060, to achieve the above-identified subject matter, so [a] gate structure is formed around the first semiconductor layers. Cheng ‘060 [0116]. Moreover, applying a known technique in the same way to enhance another known technique to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
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Regarding claim 2, Cheng as modified by Cheng ‘060 teaches the method of claim 1, and Cheng further teaches further comprising removing side portions of the first semiconductor layers (112) to form recesses on either side of the first semiconductor layers (112) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}.
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Regarding claim 3, Cheng as modified by Cheng ‘060 teaches the method of claim 2, and Cheng further teaches further comprising forming a plurality of inner spacers in the recesses on either side of the first semiconductor layers (112) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below; inner spacers formed by residual material of 112 within 132A after the removal of other material of 112 to create recesses}.
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Regarding claim 4, Cheng as modified by Cheng ‘060 teaches the method of claim 3, and Cheng further teaches wherein removing the upper portion of the substrate (102) through the second opening comprises removing a portion of the substrate (102) under (e.g., lower position) a bottom-most inner spacer of the plurality of inner spacers {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}.
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Regarding claim 5, Cheng as modified by Cheng ‘060 teaches the method of claim 3, but Cheng does not teach wherein removing the upper portion of the substrate through the second opening comprises exposing a bottom surface of a bottom-most spacer of the plurality of inner spacers.
Cheng ‘060 teaches removing an upper portion of a substrate (10/11) through an opening (59) comprises exposing a bottom surface of a bottom-most spacer (62) of a plurality of inner spacers (62) {Fig. 30B; [0106, 0107]}. The motivation for this modification is identified with respect to base claim 1.
Regarding claim 6, Cheng as modified by Cheng ‘060 teaches the method of claim 1, and Cheng further teaches wherein forming the first and second portions of the gate structure (162, 164) comprises depositing, within the first and third openings, gate layers (164) comprising a gate dielectric layer (162), a work function layer (work function layer), and a gate electrode layer (gate electrode layer) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0148, 0165]}.
Regarding claim 7, Cheng as modified by Cheng ‘060 teaches the method of claim 1, and Cheng further teaches further comprising forming the plurality of first semiconductor layers (112) of a material same as a material of the upper portion of the substrate (102) {[0019, 0024]}.
Regarding claim 8, Cheng as modified by Cheng ‘060 teaches the method of claim 1, and Cheng further teaches further comprising:
depositing the plurality of first semiconductor layers (112) comprising silicon germanium {[0024]}; and
depositing the plurality of second semiconductor layers (110) comprising silicon {[0024]}.
Regarding claim 9, Cheng teaches the method of claim 1, and Cheng further teaches further comprising:
depositing the plurality of first semiconductor layers (112) comprising silicon {[0024]}; and
depositing the plurality of second semiconductor layers (110) comprising silicon germanium {[0024]}.
Regarding claim 10, Cheng as modified by Cheng ‘060 teaches the method of claim 1, and Cheng further teaches wherein removing the upper portion of the substrate (102) through the second opening comprises etching the substrate (102) to form the third opening with an oval-shaped cross-sectional area {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}.
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Regarding claim 11, Cheng teaches a method, comprising:
depositing a plurality of alternating layers of first and second semiconductor layers (110, 112) on a substrate (102) {Figs. 1A-1, 1A-2, 4; [0019, 0023]};
etching the first semiconductor layers (112) to expose the second semiconductor layers (110), and a top surface of the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]};
etching the top surface of the substrate (102) to form an opening {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]}; and
forming a gate structure (162, 164) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}, comprising:
forming a first portion (portion of 162, 164 within first openings) of the gate structure (162, 164) wrapped around each of the second semiconductor layers (110) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}; and
forming a second portion (portion of 162, 164 within third opening) of the gate structure (162, 164) within the opening {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}.
Cheng does not teach:
forming a plurality of inner spacers on sidewalls of the first semiconductor layers;
etching the first semiconductor layers to expose the plurality of inner spacers;
the opening extends beneath a bottom-most inner spacer of the plurality of inner spacers, wherein the bottom-most inner spacer partially covers the opening.
Cheng ‘060 teaches forming a plurality of inner spacers (62) on sidewalls of first semiconductor layers (25) {Fig. 25B; [0100]}; etching the first semiconductor layers (25) to expose the plurality of inner spacers (62) {Fig. 30B; [0106, 0107]}; an opening (59 in 10/11) extends beneath (at a lower level than) a bottom-most inner spacer (62) of the plurality of inner spacers (62), wherein the bottom-most inner spacer (62) partially covers the opening (59 in 10/11) {Fig. 2A, opening in 10/11 subsequently filled by 104, 106}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng’s method based on the teachings of Cheng ‘060, as identified above, so [a] gate structure is formed around the first semiconductor layers. Cheng ‘060 [0116]. Moreover, applying a known technique in the same way to enhance another known technique to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Regarding claim 12, Cheng as modified by Cheng ‘060 teaches the method of claim 11, and Cheng further teaches further comprising forming the first semiconductor layers (112) of a material same as a material of the top surface of the substrate (102) {[0019, 0024]}.
Regarding claim 13, Cheng as modified by Cheng ‘060 teaches the method of claim 11, and Cheng further teaches wherein forming the first and second portions of the gate structure (162, 164) comprises depositing, within the opening, gate layers (164) comprising a gate dielectric layer (162), a work function layer (work function layer), and a gate electrode layer (gate electrode layer) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0148, 0165]}.
Regarding claim 14, Cheng as modified by Cheng ‘060 teaches the method of claim 11, and Cheng further teaches wherein depositing the first and second semiconductor layers (110, 112) comprises depositing germanium layers and germanium tin alloy layers, respectively {[0024]}.
Regarding claim 15, Cheng as modified by Cheng ‘060 teaches the method of claim 11, and Cheng further teaches wherein etching the top surface of the substrate (102) comprises etching the substrate (102) to form the opening with an oval-shaped cross-sectional area {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}.
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Regarding claim 16, Cheng teaches a method, comprising:
depositing first and second groups of semiconductor layers (portions of 110, 112 within 132A) to form a stack of alternating semiconductor layers (110, 112) on a substrate (102) {Figs. 1A-1, 1A-2, 4; [0019, 0023]};
removing the first group of semiconductor layers (portions of 112 within 132A), wherein a portion of a top surface of the substrate (102) and portions of the second group of semiconductor layers (portions of 110 within 132A) are exposed {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]};
forming an opening by etching the portion of the top surface of the substrate (102) that is exposed, wherein the opening extends below the top surface of the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]}; and
forming a gate structure (162, 164) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}, comprising:
forming a first portion (portion of 162, 164 within first openings) of the gate structure (162, 164) wrapped around each semiconductor layer of the second group of semiconductor layers (portions of 110 within 132A) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}; and
forming a second portion (portion of 162, 164 within third opening) of the gate structure (162, 164) in the opening {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}.
Cheng does not teach:
forming a plurality of spacers on sidewalls of the first group of semiconductor layers;
removing the first group of semiconductor layers, wherein a portion of a top surface of the substrate and portions of the second group of semiconductor layers between the plurality of spacers are exposed;
forming an opening by etching the portion of the top surface of the substrate that is exposed between the plurality of spacers,
wherein a length of the opening between two spacers of the plurality of spacers in a first direction is greater than a length of a semiconductor layer of the second group of semiconductor layers along the first direction.
Cheng ‘060 teaches forming a plurality of spacers (62) on sidewalls of a first group of semiconductor layers (25) {Fig. 25B; [0100]}; removing the first group of semiconductor layers (25) {Fig. 30B; [0106, 0107]}, wherein a portion of a top surface of a substrate (10/11) and portions of a second group of semiconductor layers (20) between the plurality of spacers (62) are exposed {Fig. 30B; [0106, 0107]}; forming an opening (59 in 10/11) by etching the portion of the top surface of the substrate (10/11) that is exposed between the plurality of spacers (62), wherein a length of the opening (59 in 10/11) between two spacers (62) of the plurality of spacers (62) in a first direction (Y) is greater than a length of a semiconductor layer (20) of the second group of semiconductor layers (20) along the first direction (Y) {Fig. 2A, opening in 10/11 subsequently filled by 104, 106}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng’s method based on the teachings of Cheng ‘060, as identified above, so [a] gate structure is formed around the first semiconductor layers. Cheng ‘060 [0116]. Moreover, applying a known technique in the same way to enhance another known technique to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Regarding claim 17, Cheng as modified by Cheng ‘060 teaches the method of claim 16, and Cheng further teaches wherein depositing the first and second groups of semiconductor layers (portions of 110, 112 within 132A) comprises depositing silicon germanium layers and silicon layers, respectively {[0024]}.
Regarding claim 18, Cheng as modified by Cheng ‘060 teaches the method of claim 16, but Cheng does not teach forming the opening comprises exposing a bottom surface of a bottom-most spacer of the plurality of spacers.
Cheng ‘060 teaches forming an opening (59) comprises exposing a bottom surface of a bottom-most spacer (62) of the plurality of spacers (62) {Fig. 30B; [0106, 0107]}. The motivation for this modification is identified with respect to base claim 16.
Regarding claim 19, Cheng as modified by Cheng ‘060 teaches the method of claim 16, and Cheng further teaches wherein depositing the first and second groups of semiconductor layers (portions of 110, 112 within 132A) comprises depositing germanium layers and germanium tin alloy layers, respectively {[0024]}.
Regarding claim 20, Cheng as modified by Cheng ‘060 teaches the method of claim 16, and Cheng further teaches wherein forming the opening comprises forming the opening with a cross-sectional area having an oval shape {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}.
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Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 30 July 2026 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
