DETAILED ACTION
Claims 1-10 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 4 and 8 are objected to because of the following informalities:
Claim 1 states “wherein A and B are positive integer”, when it should state “wherein A and B are positive integers”, to reflect that both a plurality of values (A and B) are integers. Claims 4 and 8 contain similar limitations.
Claim 4 states “the memory device acceses A of the plurality of blocks”, accesses is misspelled.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 states “wherein the specific mapping rule is to convert the blocks of the logical addresses to the N partitions through the following manner, Partition 1: Blocks 0, N, 2N, 3N,... Partition 2: Blocks 1, N+1, 2N+1, 3N+1,... Partition 3: Blocks 2, N+2, 2N+2, 3N+2,... ..., and Partition N: Blocks N-1, 2N-1, 3N-1,....” while claim 1 states “accessing A of the N blocks with continuous logical addresses as a first partition”. Claim 2 appears to describe striping consecutive logical addresses across N partitions, while claim 1 describes A consecutive logical addresses as belonging to a single partition. The claims directly contradict each other, and it is unclear how logical addresses are meant to be organized into any partition. Claims 5 and 9 contain similar limitations, and are rejected for at least the same reasons as claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 7-8 and 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hirao et al. (U.S. PGPub No. 2013/0227246)
Claim 1
Hirao (2013/0227246) teaches:
A block addressing method for a memory device, comprising:
dividing a memory array of the memory device into N partitions, wherein N is an integer; P. 0119-120 multiple logical BA groups are formed and registered in a translation table 23B; P. 0052 BA translation table 23A indicates the correspondence between logical and physical block addresses in NAND memory 4A
converting a physical address of each of a plurality of blocks of the memory device into a logical address according to a specific mapping rule, wherein there are a plurality of bad blocks in the plurality of blocks; P. 0065 block address translation unit 35A translates a logical BA into a physical BA using the BA translation table 23A and the validity management table 24A; P. 0087-88 validity management table 24A may indicate a physical block corresponding to physical BA “v+1” as invalid, and a bad block; P. 0248 each logical block has an allowable value number of defective physical blocks
addressing the blocks to the N partitions according to the logical addresses; and P. 0084-85 each logical BA group includes 16 logical BAs
accessing A of the plurality of blocks with continuous logical addresses as a first partition P. 0079 16 continuous logical BAs are formed into one logical BA group to store codes with B bad blocks tolerance, wherein A and B are positive integer, and B is smaller than A, and a number of the plurality of bad blocks included in the first partition is smaller than B. P. 0248 each logical block has an allowable value number of defective physical blocks (e.g. 2 or 4); P. 0051 a logical block is associated with one or more physical blocks; P. 0080 64 physical BAs are formed into a physical BA group set corresponding to the logical BA group
Claim 3
Hirao (2013/0227246) teaches:
The block addressing method for the memory device according to claim 1, wherein the memory device is a NAND flash memory device. P. 0050 and FIG. 1 NAND memory 4A stores read and write data from the host device 10A
Claim 4
Hirao (2013/0227246) teaches:
A memory device, comprising:
a memory array divided into N partitions, wherein N is an integer; and P. 0119-120 multiple logical BA groups are formed and registered in a translation table 23B; P. 0052 BA translation table 23A indicates the correspondence between logical and physical block addresses in NAND memory 4A
a decoder coupled to the memory array, converting a physical address of each of a plurality of blocks of the memory into a logical address according to a specific mapping rule, and P. 0065 block address translation unit 35A translates a logical BA into a physical BA using the BA translation table 23A and the validity management table 24A
addressing the blocks to the N partitions according to the logical addresses, wherein there are a plurality of bad blocks in the plurality of blocks, P. 0084-85 each logical BA group includes 16 logical BAs; P. 0051 a logical block is associated with one or more physical blocks; P. 0248 each logical block has an allowable value number of defective physical blocks
wherein when an access operation is operated, the memory device acceses A of the plurality of blocks with continuous logical addresses as a first partition to store codes, P. 0079 16 continuous logical BAs are formed into one logical BA group wherein A and B are positive integer, and B is smaller than A, and a number of the plurality of bad blocks included in the first partition is smaller than B. P. 0248 each logical block has an allowable value number of defective physical blocks (e.g. 2 or 4); P. 0080 64 physical BAs are formed into a physical BA group set corresponding to the logical BA group
Claim 7
Hirao (2013/0227246) teaches:
The memory device according to claim 4, wherein the memory device is a NAND flash memory device. P. 0050 and FIG. 1 NAND memory 4A stores read and write data from the host device 10A
Claim 8
Hirao (2013/0227246) teaches:
A block addressing method for a memory device, comprising: dividing a memory array of the memory device into N partitions, wherein N is an integer; and P. 0119-120 multiple logical BA groups are formed and registered in a translation table 23B; P. 0052 BA translation table 23A indicates the correspondence between logical and physical block addresses in NAND memory 4A
treating N blocks among a plurality of blocks of the memory device as a unit and addressing the N blocks into partitions P1 to PN one by one until all the blocks are addressed, wherein there are a plurality of bad blocks in the N blocks and. P. 0084-85 each logical BA group includes 16 logical BAs; P. 0051 a logical block is associated with one or more physical blocks; P. 0248 each logical block has an allowable value number of defective physical blocks
accessing A of the N blocks with continuous logical addresses as a first partition P. 0079 16 continuous logical BAs are formed into one logical BA group to store codes with B bad blocks tolerance, wherein A and B are positive integer, and B is smaller than A, and a number of the plurality of bad blocks included in the first partition is smaller than B. P. 0248 each logical block has an allowable value number of defective physical blocks (e.g. 2 or 4); P. 0080 64 physical BAs are formed into a physical BA group set corresponding to the logical BA group
Claim 10
Hirao (2013/0227246) teaches:
The block addressing method for the memory device according to claim 8, wherein the memory device is a NAND flash memory device. P. 0050 and FIG. 1 NAND memory 4A stores read and write data from the host device 10A
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirao et al. (U.S. PGPub No. 2013/0227246) in view of Wang et al. (U.S. PGPub No. 2011/0289255).
Claim 2
Hirao does not explicitly teach striping consecutive logical addresses across a number of partitions.
Wang (2011/0289255) teaches:
The block addressing method for the memory device according to claim 1, wherein the specific mapping rule is to convert the blocks of the logical addresses to the N partitions through the following manner,
Partition 1: Blocks 0, N, 2N, 3N,... P. 0042 and FIG. 2 data block 132A [partition 1]; P. 0043-44 store data D1 and associated logical address L1 into a physical page of data block 132A, and data D5 and associated logical address L5 into another physical page of data block 132A
Partition 2: Blocks 1, N+1, 2N+1, 3N+1,... P. 0042 and FIG. 2 data block 132B; P. 0043-44 store data D2 and associated logical address L2, and data D6 and associated logical address L6 into physical pages of data block 132B [partition 2]
Partition 3: Blocks 2, N+2, 2N+2, 3N+2,... ..., and P. 0042 and FIG. 2 data block 132C
Partition N: Blocks N-1, 2N-1, 3N-1,.... P. 0042 and FIG. 2 data block 132D
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Hirao with striping consecutive logical addresses across a number of partitions taught by Wang
The motivation being to improve the accessing speed of the flash memory module (see Wang P. 0216)
The systems of Hirao and Wang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hirao with Wang obtain the invention as recited in claim 2.
Claim 5
Wang (2011/0289255) teaches:
The memory device according to claim 4, wherein the specific mapping rule is to convert the blocks of the logical addresses to the N partitions through the following manner:
Partition 1: Blocks 0, N, 2N, 3N,... P. 0042 and FIG. 2 data block 132A [partition 1]; P. 0043-44 store data D1 and associated logical address L1 into a physical page of data block 132A, and data D5 and associated logical address L5 into another physical page of data block 132A
Partition 2: Blocks 1, N+1, 2N+1, 3N+1,... P. 0042 and FIG. 2 data block 132B; P. 0043-44 store data D2 and associated logical address L2, and data D6 and associated logical address L6 into physical pages of data block 132B [partition 2]
Partition 3: Blocks 2, N+2, 2N+2, 3N+2,... ..., and P. 0042 and FIG. 2 data block 132C
Partition N: Blocks N-1, 2N-1, 3N-1,.... P. 0042 and FIG. 2 data block 132D
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Hirao with striping consecutive logical addresses across a number of partitions taught by Wang
The motivation being to improve the accessing speed of the flash memory module (see Wang P. 0216)
The systems of Hirao and Wang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hirao with Wang obtain the invention as recited in claim 5.
Claim 9
Wang (2011/0289255) teaches:
The block addressing method for the memory device according to claim 8, wherein the rule for addressing the blocks to the N partitions is:
Partition 1: Blocks 0, N, 2N, 3N,... P. 0042 and FIG. 2 data block 132A [partition 1]; P. 0043-44 store data D1 and associated logical address L1 into a physical page of data block 132A, and data D5 and associated logical address L5 into another physical page of data block 132A
Partition 2: Blocks 1, N+1, 2N+1, 3N+1,... P. 0042 and FIG. 2 data block 132B; P. 0043-44 store data D2 and associated logical address L2, and data D6 and associated logical address L6 into physical pages of data block 132B [partition 2]
Partition 3: Blocks 2, N+2, 2N+2, 3N+2,... ..., and P. 0042 and FIG. 2 data block 132C Partition N: Blocks N-1, 2N-1, 3N-1,.... P. 0042 and FIG. 2 data block 132D
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Hirao with striping consecutive logical addresses across a number of partitions taught by Wang
The motivation being to improve the accessing speed of the flash memory module (see Wang P. 0216)
The systems of Hirao and Wang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hirao with Wang obtain the invention as recited in claim 9.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirao et al. (U.S. PGPub No. 2013/0227246) in view of Brandt et al. (U.S. PGPub No. 2020/0104068).
Claim 6
Hirao does not explicitly teach the address mapping mechanism being a row decoder.
Brandt (2020/0104068) teaches:
The memory device according to claim 4, wherein the decoder is a row decoder. P. 0023 memory sub-system 110 can include address circuitry (e.g., a row decoder and a column decoder) that can receive a logical address from the controller 115 and decode the logical address to one or more physical addresses
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Hirao with the address mapping mechanism being a row decoder taught by Brandt.
The motivation being to convert logical addresses to one or more physical addresses (see Brandt P. 0023)
The systems of Hirao and Brandt are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hirao with Brandt obtain the invention as recited in claim 6.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (U.S. PGPub No. 2014/0223079) teaches grouping logical black addresses into a plurality of logical address groups.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/STEPHANIE WU/ Primary Examiner, Art Unit 2133
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