Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Acknowledgment is made of applicant's claim for foreign priority based on an application filed in 18/789,608 on 7/30/24. It is noted, however, that applicant has not filed a certified copy of the JP2023-169719 application as required by 37 CFR 1.55.
Certified copy for the Japanese priority needs to be provided.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 7/30/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Yamamoto Yuji (JP H0983452). (“Yamamoto”, provided in the IDS).
6. Regarding claim 1, Yamamoto teaches A current detection circuit [Figures 1-10, a current detection circuit is shown], comprising: an input port [See Figure 1 below]; an output port [See Figure 1 below]; a rectifying element [See Figure 1 below, rectifying element 5 is shown]; a current control circuit, a load element [Figure 1 below, load 2 is shown]; a first transistor, which is a first conductivity type field effect transistor [Figure 1 below, a first transistor 4 is shown]; and a voltage detection circuit, comprising a voltage detection terminal and a detection result output port [Figure 1 below, a voltage detection circuit is shown], the current control circuit comprising: a first terminal, connected to a first power source terminal; and a second terminal, connected to an anode terminal of the rectifying element, a drain of the first transistor, and a voltage detection terminal of the voltage detection circuit, wherein a gate of the first transistor is configured to connect the input port and a cathode terminal of the rectifying element to a second power source terminal via the load element, and the output port is connected to a detection result output port of the voltage detection circuit [Figure 1 below shows the current control circuit comprising a first terminal, a second terminal, anode terminal, drain, gate terminals, cathode terminal arranged in a same fashion to that of current application, output port Vout also shown].
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Allowable Subject Matter
7. Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
2. The current detection circuit according to claim 1, the current control circuit comprising: a second transistor and a third transistor, which are second conductivity type field effect transistors; and a first constant current element, the first constant current element comprising: a first end, connected to a gate and a drain of the second transistor and a gate of the third transistor; and a second end, connected to the second power source terminal, wherein a source of each of the second transistor and the third transistor is connected to the first terminal, and a drain of the third transistor is connected to the second terminal.
3. The current detection circuit according to claim 1, the load element comprising: a fourth transistor, which is a first conductivity type field effect transistor, and the load element including a first end connected to a gate and a drain of the fourth transistor and a second end connected to a source of the fourth transistor.
4. The current detection circuit according to claim 1, the voltage detection circuit comprising: a fifth transistor, which is a first conductivity type field effect transistor; and a second constant current element, and wherein a first end of the second constant current element is connected to the first power source terminal, a source of the fifth transistor is connected to the second power source terminal, a gate of the fifth transistor is connected to the voltage detection terminal, and a drain of the fifth transistor is connected to a second end of the second constant current element and the detection result output port.
Allowable Subject Matter
8. Claims 5-8 are allowed.
9. The following is an examiner’s statement of reasons for allowance:
10. Regarding claim 5, the prior art of record Yamamoto teaches A current detection circuit [Figures 1-10, a current detection circuit is shown], comprising: an input port [See Figure 1 above]; an output port [See Figure 1 above]; a rectifying element [See Figure 1 above, rectifying element 5 is shown]; a current control circuit, a load element [See Figure 1 above, a load element 2 is shown]; a first transistor, which is a first conductivity type field effect transistor [Figure 1 above, a first transistor 4 is shown]; and a voltage detection circuit, comprising a voltage detection terminal and a detection result output port, the current control circuit comprising: a first terminal, connected to a first power source terminal [Figure 1 above, a voltage detection circuit is shown]; … and the output port is connected to a detection result output port of the voltage detection circuit [Figure 1 above, see output port Vout].
The prior art of record taken alone or in combination fails to teach or suggest the limitation of “and a second terminal, connected to the input port, a cathode terminal of the rectifying element, a drain of the first transistor, and a voltage detection terminal of the voltage detection circuit, and wherein a gate of the first transistor is configured to connect an anode terminal of the rectifying element to a second power source terminal via the load element” in combination with other limitations of the claim.
11. Claims 6-8 are also allowed as they further limit claim 5.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nobu Keiichiro (JP 2001356139), Figures 1-6 shows current detecting circuit comprising voltage source, transistor, diode, load arranged in a specific manner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEEL D SHAH whose telephone number is (571)270-3766. The examiner can normally be reached M-F: 9AM-5:30PM.
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/NEEL D SHAH/Primary Examiner, Art Unit 2858