Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/12/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5, 8-9, 12,15-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US Pat. Pub. 20190196959; hereinafter referred to as Ji) in view of Mozak et al. (US Pat. Pub. 20140095947; hereinafter referred to as Mozak).
As per claims 1, 8, and 15:
Ji teaches a system and a method (Ji par. 0025, memory system and method) comprising:
a memory device comprising a plurality of dies (Ji par. 0053, memory device 150); and
a processing device, coupled with the memory device (Ji par. 0053, controller 130), configured to perform operations comprising:
determining to perform a test for a subset of block stripes of a plurality of block stripes of the memory device (Ji par. 0091, evaluate super block performance grades of super blocks SP1 to SPn), wherein each block stripe of the plurality of block stripes spans the plurality of dies of the memory device (Ji par. 0065-0066, each super block spans multiple memory devices), and wherein the subset of block stripes includes less than all block stripes of the plurality of block stripes (Ji par. 0091, subsets SP1 to SPn);
Ji does not explicitly disclose a non-transitory computer-readable storage medium, obtaining a first parameter that indicates a first block stripe to be tested; obtaining a second parameter that indicates a quantity of block stripes to be tested; and initiating the test for the subset of block stripes using the first parameter and the second parameter. However, Mozak discloses a non-transitory computer-readable storage medium (Mozak par. 0098, non-transitory computer readable medium), obtaining a first parameter that indicates a first block stripe to be tested (Mozak par. 0077, identify a start address for a test); obtaining a second parameter that indicates a quantity of block stripes to be tested (Mozak par. 0077, obtain a stop address for a test. Please note a quantity parameter is inferred from the start and stop addresses); and initiating the test for the subset of block stripes using the first parameter and the second parameter (Mozak par. 0019, iterate a test sequence using a range of addresses. Please note the range of addresses includes the start and stop addresses as stated in Mozak par. 0077).
Ji and Mozak are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Mozak’s iterating a test sequence using a start and stop parameter with the system and method of Ji because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would improve efficiency by allowing the controller to focus testing on specific superblocks.
As per claims 2, 9, and 16:
Ji and Mozak further teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15, wherein the first block stripe is y and the quantity of block stripes is n, and wherein the processing device, to initiate the test for the subset of block stripes using the first parameter and the second parameter, is configured to initiate the test for all block stripes included in a range of block stripes from y to y+n-1 (Mozak par. 0077. Please note when given a starting address (y) and count (n), iterating from range y to y+n-1 is a routine, obvious procedure that would occur to any person of ordinary skill in the art, thus testing block stripes included in a range of block stripes from y to y+n-1 is merely a design choice).
As per claims 5, 12, and 19:
Ji and Mozak further teach the system of claim 1, method of claim 8, non-transitory computer-readable storage medium of claim 15, wherein the test for the subset of block stripes is included in a plurality of candidate tests, the plurality of candidate tests comprising at least a first test associated with a first subset of block stripes that begins with the first block stripe and includes the quantity of block stripes and a second test associated with a second subset of block stripes that begins with a second block stripe and that includes the quantity of block stripes. (Mozak par. 0115, multiple test sequences, each iterating through a selected range)
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ji-Mozak in further view of Hutchison et al. (US Pat. Pub. 20240118821; hereinafter referred to as Hutchison).
As per claims 3, 10, and 17:
Ji and Mozak teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15.
Ji and Mozak do not explicitly disclose wherein obtaining the first parameter comprises generating a random number that corresponds to an identifier of the first block stripe. However, Hutchison discloses wherein obtaining the first parameter comprises generating a random number that corresponds to an identifier of the first block stripe (Hutchison par. 0047, randomly select a memory die on which the write stripe starts).
It would have been obvious to one of ordinary skill in the art to combine Hutchison’s random selection of a memory die with the system, method, and non-transitory computer-readable medium of Ji-Mozak. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it would require very little processing overhead (Hutchison par. 0043).
Claims 4, 6, 11, 13, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ji-Mozak and in further view of Kim (US Pat. Pub. 20180068731).
As per claims 4, 11, and 18:
Ji and Mozak teach the system of claim 1, the method of claim 8, and the non-transitory computer-readable storage medium of claim 15.
Ji and Mozak do not explicitly disclose wherein each block stripe of the subset of block stripes includes multiple blocks that are evenly distributed on the memory device and that cover all planes of the memory device. However, Kim discloses wherein each block stripe of the subset of block stripes includes multiple blocks that are evenly distributed on the memory device and that cover all planes of the memory device (Kim Fig. 6, superblocks are evenly distributed on the memory device and covers all planes).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim’s evenly distributed superblocks with the system, method, and non-transitory computer-readable medium of Ji-Mozak because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it maximizes I/O throughput.
As per claim 6, 13, and 20:
Ji and Mozak teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15.
Ji and Mozak do not explicitly wherein each candidate test of the plurality of candidate tests uses a same block skewing parameter. However, Kim discloses wherein each candidate test of the plurality of candidate tests uses a same block skewing parameter (Kim Fig. 6, same block skewing parameter of 0).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim’s same block skewing parameter with the system, method, and non-transitory computer-readable medium of Ji-Mozak because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it ensures reliable and comparable testing results.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ji-Mozak and in further view of Marquart (US Pat. Pub. 20130044546).
As per claims 7 and 14:
Ji and Mozak teach the system of claim 1 and method of claim 8.
Ji and Mozak do not explicitly disclose wherein the test for the subset of block stripes is a short stroke test associated with an end of life behavior of the memory device. However, Marquart discloses wherein the test for the subset of block stripes is a short stroke test associated with an end of life behavior of the memory device (Marquart par. 0006, short stroking is used to determine the lifetime of a memory system).
It would have been obvious to one of ordinary skill in the art to combine Marquart’s short stroke test with the system and method of Ji-Mozak. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it would allow for testing of partitions of a memory device to determine the lifetime of the tested partitions (Marquart par. 0006).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A YANG whose telephone number is (703)756-1447. The examiner can normally be reached Monday - Friday 8:30 a.m. - 5:30 p.m. EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
Prosecution Insights