Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Joo (US Pub # 2024/0004572).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Joo teaches a memory device, comprising: a memory cell array; and a peripheral circuit coupled to the memory cell array and configured to: during an n-th loop of a program operation performed on a first memory cell in the memory cell array (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009 where program voltage increased by step voltage ISPP during program operation, control logic 320 is peripheral circuit): apply a first voltage to a first bit line coupled to a second memory cell in the memory cell array, wherein the first memory cell and the second memory cell are coupled to a first word line (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where first voltage applied to even BL during programming); discharge the first bit line to decrease a voltage of the first bit line from the first voltage to a second voltage, wherein the second voltage is lower than the first voltage (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where first voltage discharged during T3-T4, discharged voltage is lower than the first voltage); and after the first voltage is applied to the first bit line, set a second bit line to floating, wherein the second bit line is coupled to the first memory cell (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where second voltage V1_P applied to odd BL is floating).
Even though Joo teaches program operation but silent exclusively about an n-th program loop. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Joo where programmed voltage was increased by step of ISPP during multiple program operation i.e. program loop for the purpose of effectively controlling memory operations of memory array in order to improve operation margin of memory string (see paragraph 00003).
Regarding claim 2, Joo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Joo further teaches, wherein the peripheral circuit is further configured to: during an (n-i)-th loop and an (n-j)-th loop of the program operation, apply a same voltage to the first word line, wherein i and j are two integers that are greater than zero and less than n, and i is greater than j (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156).
Regarding claim 3, Joo teaches all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Joo further teaches, wherein the peripheral circuit is further configured to: during a loop before the (n-i)-th loop of the program operation: apply the second voltage to the first bit line; and apply a program voltage to the first word line coupled to the first memory cell, wherein the program voltage is smaller than the same voltage applied during the (n-i)-th loop and the (n-j)-th loop (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0170).
Regarding claim 4, Joo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Joo further teaches, wherein a programming state of the first memory cell is the highest programming state among programming states of memory cells in the memory cell array (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0150).
Regarding claim 5, Joo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Joo further teaches, wherein the second voltage is an inhibit voltage applied to the first bit line to inhibit programming of the second memory cell (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156).
Regarding claim 6, Joo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Joo further teaches, wherein the peripheral circuit is further configured to: during the n-th loop, apply a third voltage to a first select gate line coupled to a first select gate transistor to turn on the first select gate transistor, wherein the first memory cell and the first select gate transistor are coupled to the second bit line (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0151).
Regarding claim 7, Joo teaches all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Joo further teaches, wherein the peripheral circuit is further configured to: apply a fourth voltage to a second select gate line coupled to a second select gate transistor to turn off the second select gate transistor, wherein a third memory cell and the second select gate transistor are coupled to the second bit line, and the fourth voltage is lower than the third voltage (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136).
Regarding claim 8, Joo teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Joo further teaches, wherein the fourth voltage is a negative voltage (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131).
Regarding claim 9, Joo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Joo further teaches, wherein the n-th loop is the last loop of the program operation (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0130).
Regarding claim 10, Joo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Joo further teaches, wherein the peripheral circuit is further configured to: apply, during an (n-1)-th loop of the program operation, a fifth voltage to the first bit line, wherein the fifth voltage is lower than the first voltage (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0139).
Regarding claim 11, Joo teaches all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Joo further teaches, wherein a difference between the fifth voltage and the first voltage is the same as or larger than a program voltage difference between the n-th loop and the (n-1)-th loop of the program operation (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0148).
Regarding claim 12, Joo teaches all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Joo further teaches, wherein the peripheral circuit is further configured to: apply, during an (n-2)-th loop of the program operation, a sixth voltage to the first bit line, wherein the sixth voltage is lower than the fifth voltage, and a difference between the fifth voltage and the sixth voltage is lower than or equal to a difference between the first voltage and the fifth voltage (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156).
Regarding claim 13, Joo teaches all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Joo further teaches, wherein the same voltage is applied to the first word line during last two or more loops of the program operation (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136).
Regarding independent claim 14, Joo teaches a method, comprising: during an n-th loop of a program operation performed on a first memory cell in a memory cell array (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009 where program voltage increased by step voltage ISPP during program operation): applying a first voltage to a first bit line coupled to a second memory cell in the memory cell array, wherein the first memory cell and the second memory cell are coupled to a first word line (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where first voltage applied to even BL during programming); discharging the first bit line to decrease a voltage of the first bit line from the first voltage to a second voltage, wherein the second voltage is lower than the first voltage (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where first voltage discharged during T3-T4, discharged voltage is lower than the first voltage); and after the first voltage is applied to the first bit line, setting a second bit line to floating, wherein the second bit line is coupled to the first memory cell (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where second voltage V1_P applied to odd BL is floating).
Even though Joo teaches program operation but silent exclusively about an n-th program loop. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Joo where programmed voltage was increased by step of ISPP during multiple program operation i.e. program loop for the purpose of effectively controlling memory operations of memory array in order to improve operation margin of memory string (see paragraph 00003).
Regarding claim 15, Joo teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Joo further teaches, further comprising: during an (n-i)-th loop and an (n-j)-th loop of the program operation, applying a same voltage to the first word line, wherein i and j are two integers that are greater than zero and less than n, and i is greater than j (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0145).
Regarding claim 16, Joo teaches all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Joo further teaches, further comprising: during a loop before the (n-i)-th loop of the program operation: applying the second voltage to the first bit line; and applying a program voltage to the first word line coupled to the first memory cell, wherein the program voltage is smaller than the same voltage applied during the (n-i)-th loop and the (n-j)-th loop (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156).
Regarding claim 17, Joo teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Joo further teaches, wherein a programming state of the first memory cell is the highest programming state among programming states of memory cells in the memory cell array (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0152).
Regarding independent claim 18, Joo teaches a memory system, comprising: a memory device, comprising: a memory cell array; and a peripheral circuit coupled to the memory cell array and configured to perform operations comprising: during an n-th loop of a program operation performed on a first memory cell in the memory cell array (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009 where program voltage increased by step voltage ISPP during program operation): applying a first voltage to a first bit line coupled to a second memory cell in the memory cell array, wherein the first memory cell and the second memory cell are coupled to a first word line (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where first voltage applied to even BL during programming); discharging the first bit line to decrease a voltage of the first bit line from the first voltage to a second voltage, wherein the second voltage is lower than the first voltage (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where first voltage discharged during T3-T4, discharged voltage is lower than the first voltage); and after the first voltage is applied to the first bit line, setting a second bit line to floating, wherein the second bit line is coupled to the first memory cell; and a controller coupled to the memory device and configured to send one or more signals to the memory device to initiate the operations (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177 where second voltage V1_P applied to odd BL is floating).
Even though Joo teaches program operation but silent exclusively about an n-th program loop. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Joo where programmed voltage was increased by step of ISPP during multiple program operation i.e. program loop for the purpose of effectively controlling memory operations of memory array in order to improve operation margin of memory string (see paragraph 00003).
Regarding claim 19, Joo teaches all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Joo further teaches, wherein the operations further comprise: during an (n-i)-th loop and an (n-j)-th loop of the program operation, applying a same voltage to the first word line, wherein i and j are two integers that are greater than zero and less than n, and i is greater than j (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168).
Regarding claim 20, Joo teaches all claimed subject matter as applied in prior rejection of claim 19 on which this claim depends.
Joo further teaches, wherein the operations further comprise: during a loop before the (n-i)-th loop of the program operation: applying the second voltage to the first bit line; and applying a program voltage to the first word line coupled to the first memory cell, wherein the program voltage is smaller than the same voltage applied during the (n-i)-th loop and the (n-j)-th loop (see Fig. 1-6, 10-12, 17-21, paragraph 0007-0009, 0074-0079, 0092-0093, 0097-0109, 0112-0115, 0122-0131, 0136-0156, 0168-0177).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824