DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 112
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It is not clear to Examiner if “voltage regulators” in claim 11, line 8 are the same or different from “voltage regulators” in claim 15, line 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, 16, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,891,855 to Yang et al. (hereafter Yang).
Regarding independent claim 11, Yang teaches a memory system configured to attenuate supply voltage fluctuations, the memory system comprising:
a memory controller (FIG. 3A: application processor 100), including:
a voltage-threshold violation detection circuit configured to detect a supply voltage fluctuation and generate a control signal to attenuate the supply voltage fluctuation (FIG. 3A: DVFS controller 110 determining an operation status of various functional blocks of the memory device 200, see 3:58-67);
a memory device configured to store and retrieve data (FIG. 3A: memory device 200), including:
voltage regulators configured to maintain an optimal Power Integrity (PI) state (FIG. 3A: voltage adjustment unit 210); and
a channel coupling the memory controller and the memory device, wherein the channel is configured to transmit the control signal from the memory controller to the memory device (FIG. 3A: side-band channel connecting terminals 102 and 203).
Regarding dependent claim 16, Yang teaches wherein the control signal comprises a command to consume an initial amount of current in the memory device, and wherein the initial amount of current is configured to cause supply voltage fluctuations to lapse prior to the memory device actually being accessed (FIGS. 9 and 10B: when Vol_int increasing prior to Det_freq).
Regarding independent claim 20, Yang teaches a method to attenuate excessive supply voltage fluctuations in a memory subsystem comprising a memory device configured to store and retrieve data (FIG. 3A: memory device 200), as well as a Power Management Integrated Circuit (PMIC) (FIG. 6: PMIC 300), Voltage Regulators (VRs) (FIG. 6: voltage adjustment unit 210), and an inherent Power Delivery Network (PDN) (FIG. 6: comprising connections to provide voltage according to Info_Table 250, see 9:46-60), the method comprising:
detecting a supply voltage fluctuation at a voltage-threshold violation detection circuit in the memory device (FIG. 1: DVFS controller 110 determining an operation status of various functional blocks of the memory device 200, see 3:58-67),
in response to detecting the supply voltage fluctuation, generating a control signal from an interface circuit in the memory device, wherein the control signal comprises consuming an initial amount of current, or it comprises changes to a PMIC, to VRs, and to a PDN (FIG. 6: command Ctrl_vol is sent to voltage adjustment unit 210).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8, 12-13, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of US 8,816,757 to Yabbo et al. (herafter Yabbo).
Regarding independent claim 1, Yang teaches a method to attenuate excessive supply voltage fluctuations in a memory system comprising a memory controller (FIG. 1: application processor 100) and a memory device (FIG. 1: memory device 200) configured to store and retrieve data, the method comprising:
detecting a potential supply voltage fluctuation at a voltage-threshold violation detection circuit in the memory controller (FIG. 1: DVFS controller 110 determining an operation status of various functional blocks of the memory device 200, see 3:58-67),
in response to detecting the potential supply voltage fluctuation, generating a control signal from the voltage-threshold violation detection circuit (FIG. 2: DVFS controller 110 generating voltage control command as voltage control signal Ctrl_vol, see 4:11-37 and 6:46-51);
transmitting the control signal from the memory controller to the memory device (FIG. 3A: via terminals 102 and 204);
inherent decoding the control signal in the memory device (because command sent from AP 100 and memory device 200 should be decoded for actual performance); and
attenuating the potential supply voltage fluctuation to prepare for memory access (FIG. 3A: via voltage adjustment unit 210).
Yang does not teach the strikethrough limitations.
Yabbo teaches detecting a potential supply voltage fluctuation at a voltage-threshold violation detection circuit in the memory controller, wherein the potential supply voltage fluctuation corresponds to an inherent inrushing current from an initialization state or a surge of current from a switch to a busy state after staying in a long-term idle state (FIG. 2: first event predictor 210 of processing unit 206 detecting a transition from an idle to an active state of an integrated circuit 207, see 4:29-45);
Since Yang and Yabbo are both from the same field of endeavor, the purpose disclosed by Yabbo would have been recognized in the pertinent art of Yang.
It would have been obvious to a person having ordinary skill in the art before the effective filing date to recognize that switching the functional blocks of Yang’s memory device 200 from an idle state to a busy state—as suggested by Yabbo—causes potential supply voltage fluctuations that should be accounted for by Yang’s DVFS controller 110.
Regarding dependent claim 2, Yabbo implicitly teaches wherein the potential supply voltage fluctuation is detected by receiving a Power Up signal or a Reset signal from an external processor (e.g. a logic to predict a device transitioning from an idle state to an active state. Such event is seen predicted with a power up signal, see 3:63-4:12).
Regarding dependent claim 4, Yang teaches wherein the control signal is transmitted to the memory device over a channel, and wherein the channel can include a memory channel or a side-band channel independent of the memory channel (FIG. 3A: side-band channel connecting terminals 102 and 203).
Regarding dependent claim 5, Yang implicitly teaches wherein the control signal can include a Dummy Command or a Mode Register Set (MRS) command (FIG. 3A: CMD_vol is seen as dummy command).
Regarding dependent claim 6, Yang teaches wherein the control signal comprises a command to consume an initial amount of current in the memory device, and wherein the initial amount of current is configured to cause the supply voltage fluctuation to lapse prior to the memory device being accessed (FIGS. 9 and 10B: when Vol_int increasing prior to Det_freq).
Regarding dependent claim 7, Yang teaches the memory system comprises a Power Management Integrated Circuit (PMIC) (FIG. 6: PMIC 300), Voltage Regulators (VRs) (FIG. 6: voltage adjustment unit 210), and an inherent Power Delivery Network (PDN) (FIG. 6: comprising connections to provide voltage according to Info_Table 250, see 9:46-60), and wherein the control signal comprises changes to the PMIC, the VRs, or to the PDN (FIG. 6: command Ctrl_vol is sent to voltage adjustment unit 210).
Yabbo teaches a voltage regulator (FIG. 2: power regulator 202) for regulating voltage.
Regarding dependent claim 8, Yabbo teaches wherein the changes include temporarily increasing response speed (with prediction in FIG. 2) and driving ability of the VRs (by increasing voltage in FIG. 2).
Regarding dependent claim 12, Yabbo teaches detecting a potential supply voltage fluctuation at a voltage-threshold violation detection circuit in the memory controller, wherein the potential supply voltage fluctuation corresponds to an inherent inrushing current from an initialization state or a surge of current from a switch to a busy state after staying in a long-term idle state (FIG. 2: first event predictor 210 of processing unit 206 detecting a transition from an idle to an active state of an integrated circuit 207, see 4:29-45);
Since Yang and Yabbo are both from the same field of endeavor, the purpose disclosed by Yabbo would have been recognized in the pertinent art of Yang.
It would have been obvious to a person having ordinary skill in the art before the effective filing date to recognize that switching the functional blocks of Yang’s memory device 200 from an idle state to a busy state—as suggested by Yabbo—causes potential supply voltage fluctuations that should be accounted for by Yang’s DVFS controller 110.
Regarding dependent claim 13, Yabbo implicitly teaches wherein the potential supply voltage fluctuation is detected by receiving a Power Up signal or a Reset signal from an external processor (e.g. a logic to predict a device transitioning from an idle state to an active state. Such event is seen predicted with a power up signal, see 3:63-4:12).
Regarding dependent claim 17, Yang implicitly teaches wherein the channel comprises a memory channel or a side-band channel independent of a memory channel, and wherein the control signal comprises a Dummy Command or a Mode Register Set (MRS) command (FIG. 3A: CMD_vol is seen as dummy command).
Claims 9, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Yabbo in view of US 7,355,435 to Ferraiolo et al. (hereafter Ferraiolo).
Yang and Yabbo teach, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 9, Ferraiolo teaches a method comprising an on-chip sensor to detect power supply vulnerabilities. The method comprises adjusting voltage training to attenuate supply voltage fluctuations, and wherein supply voltage fluctuations are used to determine values insensitive to such fluctuations for training cycles (FIG. 1: via VDD insensitive delay chain 104) and timing of the voltage-threshold violation detection circuit (FIG. 1: via delay chain 116).
Since Yang, Yabbo and Ferraiolo are all from the same field of endeavor, the purpose disclosed by Ferraiolo would have been recognized in the pertinent art of Yabbo.
It would have been obvious to a person having ordinary skill in the art before the effective filing date to include an on-chip sensor to detect power supply vulnerabilities as suggested in Ferraiolo to the voltage adjustment unit of Yabbo in order to better regulating power supply with unintended fluctuation.
Regarding dependent claim 19, see rejection applied to claim 9 above.
Allowable Subject Matter
Claims 3, 10, 14, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 3: wherein the surge of current is detected by measuring idle time following a most recent surge in current.
With respect to dependent claim 10: wherein measuring idle time following a most recent surge in current includes counting a number of clock cycles during which the memory device is idle, and wherein generating the control signal further comprises: determining if the number of idle clock cycles prior to the supply voltage fluctuation exceeds a threshold; and generating the control signal based on the determination.
With respect to dependent claim 14: wherein the surge of current from a switch to a busy state after staying in a long-term idle state is detected by counting a number of idle clock cycles following a most recent surge in current.
With respect to dependent claim 18: wherein the voltage-threshold violation detection circuit is further configured to detect surging current from a switch to a busy state after staying in a long-term idle state by measuring idle time following a most recent surge in current.
Conclusion
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February 24, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824