Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18789710 filed on 07/31/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 8-9, 11-12, 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang et al. (US 2024/0413040).
Regarding Independent claim 1, Yang et al. teach a package structure, comprising:
a first circuit substrate (Fig. 1, element 102, paragraph 0047) having a first side and a second side opposite to each other;
a control circuit chip (Fig. 1, element 202, paragraph 0047, 0069) disposed on the first side of the first circuit substrate and electrically connected to the first circuit substrate;
a memory chip (Fig. 1, element 201, paragraph 0047, 0057) disposed on the second side of the first circuit substrate and electrically connected to the first circuit substrate;
a second circuit substrate (Fig. 1, element 101, paragraph 0047) having a third side and a fourth side opposite to each other, wherein the memory chip is located between the second side of the first circuit substrate and the third side of the second circuit substrate (Fig. 1);
a plurality of conductive elements (Fig. 1, element 209, paragraph 0047) disposed between the second side of the first circuit substrate and the third side of the second circuit substrate and electrically connected to the first circuit substrate and the second circuit substrate;
a molding compound (Fig. 1, element 111, paragraph 0061) disposed between the second side of the first circuit substrate and the third side of the second circuit substrate and covering the memory chip and the conductive elements; and
a plurality of solder balls (Fig. 1, element 105, paragraph 0065) disposed on the fourth side of the second circuit substrate and electrically connected to the second circuit substrate.
Regarding claims 2 & 12, Yang et al. teach wherein the control circuit chip comprises an application-specific integrated circuit chip (paragraph 0069), and the memory chip comprises a double data rate synchronous dynamic random-access memory (paragraph 0057).
Regarding claims 8 & 18, Yang et al. teach wherein each of the conductive elements comprises a solder ball, a metal pillar, or a solder covering a metal ball (paragraph 0086).
Regarding claims 9 & 19, Yang et al. teach a heat dissipation block (Fig. 1, element 301, paragraph 0015, paragraph 0047) disposed on a back surface of the control circuit chip relatively far away from the first circuit substrate.
Regarding Independent claim 11, Yang et al. teach a manufacturing method of a package structure, comprising:
providing a first circuit substrate Fig. 1, element 102, paragraph 0047), wherein the first circuit substrate has a first side and a second side opposite to each other;
providing a control circuit chip (Fig. 1, element 202, paragraph 0047, 0069) and a memory chip (Fig. 1, element 201, paragraph 0047, 0057),
wherein the control circuit chip is disposed on the first side of the first circuit substrate and electrically connected to the first circuit substrate, and the memory chip is disposed on the second side of the first circuit substrate and electrically connected to the first circuit substrate (Fig. 1);
providing a second circuit substrate (Fig. 1, element 101, paragraph 0047), wherein the second circuit substrate has a third side and a fourth side opposite to each other, and the memory chip is located between the second side of the first circuit substrate and the third side of the second circuit substrate (Fig. 1);
forming a plurality of conductive elements (Fig. 1, element 209, paragraph 0047) between the second side of the first circuit substrate and the third side of the second circuit substrate, wherein the conductive elements are electrically connected to the first circuit substrate and the second circuit substrate;
forming a molding compound (Fig. 1, element 111, paragraph 0061) between the second side of the first circuit substrate and the third side of the second circuit substrate to cover the memory chip and the conductive elements; and
forming a plurality of solder balls (Fig. 1, element 105, paragraph 0065) on the fourth side of the second circuit substrate, wherein the plurality of solder balls are electrically connected to the second circuit substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2024/0413040) in view of Choi et al. (US 2025/0046769).
Regarding claims 3 & 13, Yang et al. teach a plurality of solder bumps (Fig. 1, element 208, paragraph 0070) disposed between the control circuit chip and the first circuit substrate, wherein the control circuit chip comprises a plurality of pads (Fig. 1, element 107, paragraph 0055).
Yang et al. do not explicitly disclose the pads are electrically connected to the first circuit substrate via the solder bumps.
Choi et al. teach a packaging device comprising a chip (Fig. 5, element 712, paragraph 0031) with pads (Fig. 5, element 720, paragraph 0031) and the pads are electrically connected to the first circuit substrate (Fig. 5, elements 620, 630 & 640, paragraph 0025) via the solder bumps (Fig. 5, element 730, paragraph 0037).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Yang et al. according to the teachings of Choi et al. with the motivation to provide interconnection between the chip and the first circuit substrate.
As such the exact placements of pads and solder bumps of a chip in relation to a substrate is a prima facie case of obviousness as shown by Choi et al.
Regarding claims 4 & 14, Yang et al. teach an underfill (Fig. 1, element 204, paragraph 0066) disposed between the control circuit chip and the first circuit substrate and covering the pads and the solder bumps.
Claims 5-6, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2024/0413040) in view of Chen et al. (US 2024/0063130) and further in view of Choi et al. (US 2025/0046769).
Regarding claims 5 & 15, Yang et al. teach the memory chip and first substrate.
Yang et al. do not explicitly disclose a plurality of solder bumps disposed between the memory chip and the first circuit substrate, wherein the memory chip comprises a plurality of pads, and the pads are electrically connected to the first circuit substrate via the solder bumps.
Chen et al. teach a packaging device comprising a plurality of solder bumps (Fig. 19, element 140, paragraph 0034) disposed between the chip (Fig. 19, element 138, paragraph 0034) and the first circuit substrate (Fig. 19, element 110, paragraph 0017), wherein the memory chip comprises a plurality of pads (Fig. 19, element 117b, paragraph 0021).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Yang et al. according to the teachings of Chen et al. with the motivation to provide interconnection.
Yang et al. modified by Chen et al. do not explicitly disclose the pads are electrically connected to the first circuit substrate via the solder bumps.
Choi et al. teach a packaging device comprising a chip (Fig. 5, element 712, paragraph 0031) with pads (Fig. 5, element 720, paragraph 0031) and the pads are electrically connected to the first circuit substrate (Fig. 5, elements 620, 630 & 640, paragraph 0025) via the solder bumps (Fig. 5, element 730, paragraph 0037).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Yang et al. and Chen et al. according to the teachings of Choi et al. with the motivation to provide interconnection between the chip and the first circuit substrate.
As such the exact placements of pads and solder bumps of a chip in relation to a substrate is a prima facie case of obviousness as shown by Choi et al.
Regarding claims 6 & 16, Yang et al. teach an underfill (Fig. 1, element 204, paragraph 0066) disposed between the memory chip and the first circuit substrate and covering the pads and the solder bumps.
Claims 7, 10, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2024/0413040) in view of Park et al. (US 2025/0259971).
Regarding claims 7 & 17, Yang et al. teach the memory chip.
Yang et al. do not explicitly disclose a plurality of wires disposed between the memory chip and the first circuit substrate, wherein the memory chip is electrically connected to the first circuit substrate via the wires.
Park et al. teach a packaging device comprising a plurality of wires (Fig. 2C, element 171d, paragraph 0078 discloses wire bond) disposed between the chip (Fig. 2C, element 172, paragraph 0078) and the first circuit substrate (Fig. 2C, element 171, paragraph 0071), wherein the chip is electrically connected to the first circuit substrate via the wires (Fig. 2C).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Yang et al. according to the teachings of Park et al. with the motivation to provide interconnection between the chip and the first circuit substrate.
Claims 10, 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2024/0413040) in view of Park et al. (US 2025/0259971).
Regarding claims 10 & 20, Yang et al. do not explicitly disclose wherein an orthographic projection of the control circuit chip on the first circuit substrate is completely overlapped with an orthographic projection of the memory chip on the first circuit substrate.
Park et al. teach a packaging device wherein an orthographic projection of the top chip (Fig. 2C, element 172, paragraph 0078) on the first circuit substrate (Fig. 2C, element 171, paragraph 0071) is completely overlapped with an orthographic projection of the chip (Fig. 2C, element 130, paragraph 0062) on the first circuit substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Yang et al. according to the teachings of Park et al. with the motivation to provide interconnection between chips through the first circuit substrate.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
Prosecution Insights