Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/02/2024 is being considered by the examiner.
Claim Objections
Claim 1 objected to because of the following informalities:
".
Appropriate correction is required.
Claim 5 objected to because of the following informalities:
“Forth dielectric layer” is a typographical error and to be understood as “fourth dielectric layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 2019/0164975 A1) in view of Yoon et al. (US 2012/0276711 A1) and Song et al. (US 2018/0174971 A1).
Regarding claim 1, Song et al. (US 2019/0164975 A1) teaches method of manufacturing a semiconductor memory device (FIG. 1B), comprising:
providing a substrate (100);
forming word lines (WL) extending in a first direction (second direction D2) in said substrate;
forming bit lines (BL) extending in a second direction (third direction D3) over said word lines;
forming partition structures (insulation fences 40) between said bit lines and right above (FIG. 1B) said word lines;
forming storage node contacts (BC) in spaces defined by ([0048]) said bit lines and said partition structures, wherein a portion of each of said storage node contacts protruding (FIG. 1B) from top surfaces of said bit lines and said partition structures is a contact pad (landing pad LP);
Song et al. (US 2019/0164975 A1) does not teach forming a first dielectric layer on said contact pads, said bit lines and said partition structures; forming a second dielectric layer on said first dielectric layer; and performing an etch back process to remove parts of said second dielectric layer, so that only parts of said second dielectric layer on sidewalls of said contact pads remain.
However, Yoon et al. teaches
forming a first dielectric layer (first spacer layer 140A, formed of nitride ([0025])) on said contact pads (storage node contact plugs 120A and 120B), said bit lines (first and second bit lines 175 and 180) and said partition structures (isolation layer 105);
forming a sacrifice layer (150) on said first dielectric layer; and
performing an etch back process ([0037]) to remove parts (upper surface of first spacer layer 140A and bottom surface of bit-line trench 135) of said sacrifice layer, so that only parts of said sacrifice layer on sidewalls of said contact pads remain (FIG. 7).
Yoon et al. does not expressly disclose a second dielectric layer, as the sacrifice layer taught is not of dielectric material. However, Song et al. (US 2018/0174971 A1) teaches a second dielectric layer (sacrificial spacer layer 303), formed sequentially with first spacer layer (301), and comprising silicon oxide ([0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the dielectric spacer layer of Song et al. (US 2018/0174971 A1) to the air gap structure of Yoon et al. as the intermediate layer, and to have further incorporated the air gap process and spacer stack arrangement of Yoon et al., as modified by Song et al. (US 2018/0174971 A1), into the analogous DRAM manufacturing structure of Song et al. (US 2019/0164975 A1) to obtain the predictable benefit of electrical isolation and reduced parasitic capacitance for faster and more reliable memory device performance.
Regarding claim 2, Song et al. (US 2019/0164975 A1) in view of Yoon et al. and Song et al. (US 2018/0174971 A1) teaches the method of manufacturing a semiconductor memory device of claim 1. Yoon et al. teaches further comprising:
after said etch back process ([0037]), forming a third dielectric layer (second spacer layers 155A or 155B) covering (FIG. 8) said sacrifice layer (150) and filling up spaces between (FIG. 8) said contact pads (storage node contact plugs 120A and 120B), so that said first dielectric layer (first spacer layer 140A), said second dielectric layer and said sacrifice layer collectively constitute contact pad isolation structures (FIG. 8) between said contact pads.
Yoon et al. does not expressly disclose a second dielectric layer. However, Song et al. (US 2018/0174971 A1) teaches a second dielectric layer (sacrificial spacer layer 303), covered by second spacer layer (305) and comprising silicon oxide ([0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the dielectric spacer layer of Song et al. (US 2018/0174971 A1) to the air gap structure of Yoon et al. as the intermediate layer, and to have used the dielectric spacer of the air gap structure of Yoon et al. as modified by Song et al. (US 2018/0174971 A1) to provide a dielectric isolation structure around the contact (landing) pad of Song et al. (US 2019/0164975 A1), which is to be used to later define the air gap. Surrounding the contact pads with lower-k structures reduces parasitic coupling of device between adjacent pads, thereby improving device performance in dense memory-cell layouts.
Regarding claim 3, Song et al. (US 2019/0164975 A1) in view of Yoon et al. and Song et al. (US 2018/0174971 A1) teaches the method of manufacturing a semiconductor memory device of claim 1. Yoon et al. teaches further comprising:
after said etch back process ([0037]), forming a third dielectric layer (second spacer layers 155A or 155B) filling up spaces between (FIG. 8) said contact pads (storage node contact plugs 120A and 120B), wherein said sacrifice layer (150) is exposed from (FIG. 11 and [0042], portion `A) said third dielectric layer.
Yoon et al. does not expressly disclose a second dielectric layer. However, Song et al. (US 2018/0174971 A1) teaches a second dielectric layer (sacrificial spacer layer 303, subsequently etched to sacrificial spacer 303a) exposed from second spacer SP2 (previously second spacer layer 305, comprising silicon nitride).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the dielectric spacer layer of Song et al. (US 2018/0174971 A1) to the air gap structure of Yoon et al. as the intermediate layer, and to further have formed such intermediate dielectric layer of Song et al. (US 2018/0174971 A1) as separately accessible for subsequent selective etching through the second spacer layer of Yoon et al. to improve electrical isolation around storage node contact pads.
Regarding claim 4, Song et al. (US 2019/0164975 A1) in view of Yoon et al. and Song et al. (US 2018/0174971 A1) teaches the method of manufacturing a semiconductor memory device of claim 3. Yoon et al. teaches further comprising:
removing ([0043]) said exposed sacrifice layer (150) to form air gaps (185) between (FIG. 12) said first dielectric layer (first spacer layer 140A) and said third dielectric layer (second spacer layers 155A or 155B).
Yoon et al. does not expressly disclose a second dielectric layer. However, Song et al. (US 2018/0174971 A1) teaches a second dielectric layer (sacrificial spacer layer 303), removed to cover over with capping patterns and thereby define air spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the dielectric spacer layer of Song et al. (US 2018/0174971 A1) to the air gap structure of Yoon et al. as the intermediate layer, and to have further implemented the selective removal process of intermediate layer, as taught by Yoon et al., into the analogous DRAM environment and spacer structure of Song et al. (US 2018/0174971 A1) to create air gap and thereby reduce parasitic capacitance between adjacent contact pads.
Regarding claim 5, Song et al. (US 2019/0164975 A1) in view of Yoon et al. and Song et al. (US 2018/0174971 A1) teaches the method of manufacturing a semiconductor memory device of claim 4. Yoon et al. teaches further comprising:
covering ([0046]) a fourth dielectric layer (capping layer 190, formed of nitride ([0025])) on said first dielectric layer (first spacer layer 140A), said third dielectric layer (second spacer layers 155A or 155B) and said air gaps (185) so that said air gaps are transformed into voids ([0046], sealing air gap), and said first dielectric layer, said third dielectric layer, said fourth dielectric layer and said voids collectively constitute contact pad isolation structures between said contact pads (storage node contact plugs 120A and 120B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the dielectric spacer layer of Song et al. (US 2018/0174971 A1) to the air gap structure of Yoon et al. as the intermediate layer. Yoon et al. expressly teaches a capping layer to seal the air gap formed, and Song et al. (US 2018/0174971 A1) analogously forms capping patterns contacting and closing on the top portions of air spacer, thereby defining voids, which lower effective dielectric constant and thereby reduce parasitic capacitance.
Conclusion
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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