Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 31, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 12, 19
b. Pending: 1-4, 6-7, 9-15, 18-24
Claims 5, 8, 16-17, and 25-30 have been canceled through preliminary amendments.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on December 12, 2023. It is noted, however, that applicant has not filed a certified copy of the KR10-2023-0180105 application as required by 37 CFR 1.55. Retrieval of the priority document failed on May 12, 2025, as indicated by a Failure Status Report.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "a capacitance of the decoupling capacitor" in the last two lines on page 3. There is insufficient antecedent basis for this limitation in the claim. Because claim 1 includes “a capacitance of a decoupling capacitor,” the limitation in claim 11 should read “the capacitance of the decoupling capacitor.” The penultimate line of page 3 also teaches “the first capacitance,” but there is no antecedent basis for this phrase.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US Pub. 20200402592 A1; “Shin”) in view of Li et al. (US Pub. 20170040995 A1; “Li”) and Wada (JP 2012169841 A).
Regarding independent claim 1, Shin discloses an output driver (Fig. 2: data output circuit 100; [0041]), comprising:
a selection circuit (operating signal generator 120; [0041]) configured to selectively output either a first pull-up driving signal (pull-up operating signal OP_U; [0043]: The operating signal generator 120 may output the pull-up operating signal OP_U) or a pulse signal, in response to a received first control signal ([0039]: The data input/output circuit 10 may include a data output circuit 100 that operates according to the output control signal CTRL_O output by the control logic 60; per Fig. 2, operating signal generator 120 is part of data output circuit 100, which is controlled by output control signal CTRL_O);
a first pull-up driver circuit (Fig. 3: first pull-up driver PU; [0047]) configured to provide a first supply voltage (first power supply voltage VDDQ_P; [0047]) to a first node (node N; [0047]) electrically connected to a data pin ([0146]: Each of the peripheral circuit region PERI and the memory cell region CELL of the memory device 900 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA; [0005]: a peripheral circuit region including a second metal pad, an output driver to output a data signal, and an operating signal generator to generate a plurality of operating signals for operating the output driver, and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the output driver includes: a pull-up driver including a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors; and a pull-down driver having a plurality of N-type transistors. Examiner concludes that the signals generated by the pull-up and pull-down circuits are connected to pads), in response to the first pull-up driving signal received from the selection circuit ([0052]: The pull-up operating signal OP_U includes a plurality of first pull-up operating signals OP PU0 through OP PUk input to the 0th through k.sup.th pull-up transistors PU0 through PUk of the first pull-up driver PU and a plurality of second pull-up operating signals OP NU0 through OP_NU1 input to the 0.sup.th through 1.sup.th pull-up transistors NU0 through NU1 of the second pull-up driver NU; also see pull-up operating signal OP_U in Fig. 2);
a first pull-up driver circuit (Fig. 3: first pull-up driver PU; [0047]) configured to provide a first supply voltage (first power supply voltage VDDQ_P; [0047]) in response to the first pull-up driving signal ([0052]: The pull-up operating signal OP_U includes a plurality of first pull-up operating signals OP PU0 through OP PUk input to the 0th through k.sup.th pull-up transistors PU0 through PUk of the first pull-up driver PU) or the pulse signal received from the selection circuit (Fig. 2: 120);
a second pull-up driver circuit (Fig. 3: second pull-up driver NU; [0047]) configured to provide a second supply voltage (second power supply voltage VDDQ_N; [0047]) having a second level, which is less than or equal to a first level of the first supply voltage ([0047]: the first power supply voltage VDDQ_P and the second power supply voltage VDDQ_N may have a same level or may have different levels. For example, the voltage level of the first power supply voltage VDDQ_P may be higher than that of the second power supply voltage VDDQ_N), to the first node (node N), in response to a second pull-up driving signal (second pull-up operating signals OP_NU0; [0053]);
a pull-down driver circuit (Fig. 3: pull-down driver 113; [0050]) configured to provide the third supply voltage (ground voltage VSS; [0050]) to the first node (N), in response to a pull-down driving signal ([0054]: The ON and OFF states of the 0.sup.th through m.sup.th transistors ND0 through NDm may be switched according to the pull-down operating signal OP_D input to the pull-down driver 113. The pull-down operating signal OP_D may include a plurality of pull-down operating signals OP ND0 through OP_NDm respectively input to the 0.sup.th through m.sup.th pull-down transistors ND0 through NDm).
Shin does not disclose:
a first decoupling capacitor having a first terminal electrically connected to a second node to which the second supply voltage is applied and a second terminal electrically connected to a line to which a third supply voltage is applied, said third supply voltage having a third level less than the first and second levels;
a capacitance optimization circuit configured to change a capacitance of a decoupling capacitor having a first terminal electrically connected to a third node to which the first supply voltage is applied, in response to a received second control signal; and
However, Li teaches:
a first decoupling capacitor (Fig. 2: decoupling capacitor in Cdie unit 210-1; [0027]) having a first terminal electrically connected to a second node to which the second supply voltage is applied (the top plate of the capacitor is connected to VDD1) and a second terminal electrically connected to a line to which a third supply voltage is applied (the bottom plate is connected to VSS), said third supply voltage having a third level less than the first and second levels ([0020]: a first power line VDD1 having a supply voltage VDD1 and a reference line having a predetermined reference voltage (e.g. a reference voltage VSS); [0022]: the supply voltage VDD1 at the first power line VDD1 and the supply voltage VDD2 at the second power line VDD2 may be different. For example, the supply voltage VDD2 at the second power line VDD2 (e.g. 1.1 Volts (V)) may be higher than the supply voltage VDD1 at the first power line VDD1 (e.g. 0.4 V). Examiner concludes that VDD1 and VDD2 are higher than VSS);
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Li to Shin wherein the output driver comprises: a first decoupling capacitor having a first terminal electrically connected to a second node to which the second supply voltage is applied and a second terminal electrically connected to a line to which a third supply voltage is applied, said third supply voltage having a third level less than the first and second levels in order to improve I/O signal control and prevent the supply voltage from damaging decoupling capacitors (Li, [0024]).
Also, through Wada:
a capacitance optimization circuit (Fig. 3: control circuit 36; [0037]) configured to change a capacitance of a decoupling capacitor ([0037]: As shown in FIG. 3, the system device 21 includes a control circuit 36 that controls the capacitance value of the variable capacitor 35 .) having a first terminal electrically connected to a third node (node connecting capacitor 35 to the first power supply line 21a; see annotated screenshot below) to which the first supply voltage (21a) is applied, in response to a received second control signal ([0040]: Based on the set value output from the TM determination circuit 52, the training control circuit 51 outputs a control signal SC1 for controlling the capacitance value of the variable capacitor 35); and
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It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Wada to modified Shin wherein the output driver comprises: a capacitance optimization circuit configured to change a capacitance of a decoupling capacitor having a first terminal electrically connected to a third node to which the first supply voltage is applied, in response to a received second control signal in order to reduce noise in power supply voltages and prevent the reduction of the timing margin (Wada, [0097]).
Regarding claim 7, Shin, Li, and Wada together disclose all the limitations of claim 1, and further through Shin:
wherein the second pull-up driver circuit (Fig. 3: NU) includes a second N-type transistor (pull-up transistor NU0; [0049]) including a first electrode to which the second supply voltage (VDDQ_N) is applied, a second electrode electrically connected to the first node (N), and a gate electrode to which the second pull-up driving signal (OP_NU0) is applied.
Regarding claim 10, Shin, Li, and Wada together disclose all the limitations of claim 1, and further through Shin:
wherein the selection circuit (Fig. 2: 120) is configured to output the first pull-up driving signal (OP_U) to the first pull-up driver circuit (Fig. 3: PU);
wherein the first pull-up driver circuit is configured to electrically connect the first node (N) to the third node (N3, see annotated screenshot below) during a pull-up period;
wherein the second pull-up driver circuit (NU) is configured to electrically connect the first node (N) to the second node (N2, see annotated screenshot below) during the pull-up period; and
wherein the second level is equal to the first level ([0047]: the first power supply voltage VDDQ_P and the second power supply voltage VDDQ_N may have a same level or may have different levels).
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US Pub. 20200402592 A1), Li (US Pub. 20170040995 A1), and Wada (JP 2012169841 A) as applied to claim 1 above, and further in view of Maruyama et al. (US Pub. 20020038914 A1; “Maruyama”).
Regarding claim 2, Shin, Li, and Wada together disclose all the limitations of claim 1. Neither Shin, Li, nor Wada discloses:
wherein the capacitance optimization circuit includes:
a second decoupling capacitor electrically connected between the third node and the line;
a third decoupling capacitor electrically connected between a fourth node, which is electrically connected to a logic circuit, and the line; and
a switch configured to electrically connect the third node to the fourth node based on the second control signal.
However, Maruyama teaches:
wherein the capacitance optimization circuit (Fig. 1: pin capacitance adjustment circuit; [0046]) includes:
a second decoupling capacitor (capacitor C11; [0046]) electrically connected between the third node (electrode N1; [0046]) and the line (ground potential VSS; [0046]);
a third decoupling capacitor (C10; [0050]) electrically connected between a fourth node (see annotated screenshot below), which is electrically connected to a logic circuit (input circuit and output circuit. Examiner asserts that input/output circuits usually contain logic components), and the line (VSS); and
a switch (CMOS type transfer gate circuit FER-1; [0046]) configured to electrically connect the third node to the fourth node based on the second control signal (output CADD; [0046]: CMOS type transfer gate circuit FER-1 comprising an NMOS transistor Nch-1 to which an output CADD of the OR circuit OR-1 is input, and a PMOS transistor Pch-3 to which bCADD reversed by the output CADD is reversed by the inverter circuit INV3; [0008]: the output ".times.4e" of the inverter circuit INV1 is set to the "HIGH" level so that the setting of the structure is changed over to the ".times.4 bit" constitution through the bit configuration change-over control circuit. Examiner asserts that CADD may be a control signal, and it is controlled by control signals).
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It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maruyama to modified Shin wherein the capacitance optimization circuit includes: a second decoupling capacitor electrically connected between the third node and the line; a third decoupling capacitor electrically connected between a fourth node, which is electrically connected to a logic circuit, and the line; and a switch configured to electrically connect the third node to the fourth node based on the second control signal in order to provide a circuit that adjusts the capacitance between pins based on the bit configuration without requiring a special wiring mask (Maruyama, [0041]-[0042]).
Allowable Subject Matter
Claims 12-15 and 18-24 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claims 12 and 19 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
“a second capacitance that is greater than or equal to the first capacitance”
“an equalizer configured to output the pulse signal based on a sixth control signal”.
The Examiner was not able to find additional references to logically combine with Shin, Li, Wada, and Maruyama in order to reject the other above features of claims 12 and 19. Refer to conclusion section for relevant references.
Claims 3, 4, 6, 9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mahmoodi et al. (US Pub. 20240428860 A1): paras. [0161]-[0163] and Fig. 7A are relevant to claims 12 and 19. In Fig. 7A, 706 is an equalization circuit with a pulse output, which is relevant to the last limitation of claims 12 and 19. Also, 718a and 719a are multiplexers, but Mahmoodi does not teach the multiplexer outputting a pulse signal received from the equalization circuit, nor a pull-up driving signal.
Kim (US Pub. 20010052811 A1): para. [0056] and Fig. 7 are relevant to claim 3.
Arora et al. (US Pub. 20230402976 A1): paras. [0079], [0085], [0087], [0106], and Fig. 5 are relevant to claim 4.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
2/20/2026