DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 12, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 12, and 19 recite, using claim 1 for example language, “configure… the stream processor to provide data with the memory device at the first latency” and “configure… the scheduling processor to provide the data with one or more memory registers of the second processor at the second latency”. The preposition “with” creates an indefiniteness issue, as “providing A with B” means that item A receives B, which results in a nonsensical interpretation. For the purpose of examination, while no language amendment is suggested, it is assumed that the memory device/memory registers receive the data, instead of the opposite as currently recited.
The dependent claims are rejected for dependence on one of the independent claims.
Claims 5 and 16 recite, using claim 5 for example language, “based on at least one of the dimension of the memory device…”, but “the dimension of the memory device” lacks proper antecedent basis, as this is the first recitation of the limitation in either the instant claim or their respective parent claims. For the purpose of examination, it is assumed that the claims recite “based on at least one of a dimension of the memory device…”
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1, 12, and 19 recite, using claim 1 for example language,
a first processor including a stream processor and a scheduling processor, the first processor coupled with the memory device;
one or more processors to:
configure, according to a first latency of the memory device, the stream processor to provide data with the memory device at the first latency;
configure, according to a second latency of the second processor, the scheduling processor to provide the data with one or more memory registers of the second processor at the second latency;
provide the data between the first processor and the memory device at the first latency; and
provide the data between the second processor and the stream processor at the second latency.
The concept of memory of different tiers/locations having different access latencies is not novel, see Hutsell et al. (US 7,664,907), Singh et al. (US 7,836,229), Wegener (US 2013/0262809), Corsi et al. (US 2020/0110639), Wegener (WO 2013/149045),with Wegener in particular identifying how latencies are different between memories that are in the same integrated circuit as a processor and memories that are not in the same integrated circuit as a processor, and Corsi in particular identifying different latencies in a multi-core system. However, none of the references found provide for two sub-processors within a single processor, where the two sub-processors interact with different elements at different latencies, let alone the specific memory registers of the second, separate processor as claimed.
This leads to a determination of allowable subject matter.
Examiner notes that claim 19 recites a slightly broader scope, as it does not recite the specific streaming processor/scheduling processor within the first processor seen in claims 1 and 12. However, no reference was found to provide the different latency configuration as discussed above, and as such the discussion above still applies to claim 19.
The dependent claims are indicated to recite allowable subject matter for dependence on one of the independent claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hutsell, Singh, Wegener, Corsi, Wegener, as cited above,
Reghunath et al. (US 10,534,736), Cai et al. (US 2019/0034239), Polychroniou et al. (US 2019/0377683), disclose relating buffer sizes with memory latency,
Kotra et al. (US 2022/0100665) discloses moving data between registers and memory, but does not disclose the registers as being found in a separate processor from a control/operative core.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON D HO whose telephone number is (469)295-9093. The examiner can normally be reached Mon-Fri 8:00-4:00 CT.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139