Prosecution Insights
Last updated: April 18, 2026
Application No. 18/789,896

LOAD AND STORE MEMORY ARCHITECTURE

Non-Final OA §112
Filed
Jul 31, 2024
Examiner
HO, AARON D
Art Unit
2139
Tech Center
2100 — Computer Architecture & Software
Assignee
Nvidia Corporation
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
187 granted / 251 resolved
+19.5% vs TC avg
Strong +15% interview lift
Without
With
+15.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
11 currently pending
Career history
262
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
13.6%
-26.4% vs TC avg
§112
23.0%
-17.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 251 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on February 12, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1, 12, and 19 recite, using claim 1 for example language, “configure… the stream processor to provide data with the memory device at the first latency” and “configure… the scheduling processor to provide the data with one or more memory registers of the second processor at the second latency”. The preposition “with” creates an indefiniteness issue, as “providing A with B” means that item A receives B, which results in a nonsensical interpretation. For the purpose of examination, while no language amendment is suggested, it is assumed that the memory device/memory registers receive the data, instead of the opposite as currently recited. The dependent claims are rejected for dependence on one of the independent claims. Claims 5 and 16 recite, using claim 5 for example language, “based on at least one of the dimension of the memory device…”, but “the dimension of the memory device” lacks proper antecedent basis, as this is the first recitation of the limitation in either the instant claim or their respective parent claims. For the purpose of examination, it is assumed that the claims recite “based on at least one of a dimension of the memory device…” Allowable Subject Matter Claims 1-20 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: Claims 1, 12, and 19 recite, using claim 1 for example language, a first processor including a stream processor and a scheduling processor, the first processor coupled with the memory device; one or more processors to: configure, according to a first latency of the memory device, the stream processor to provide data with the memory device at the first latency; configure, according to a second latency of the second processor, the scheduling processor to provide the data with one or more memory registers of the second processor at the second latency; provide the data between the first processor and the memory device at the first latency; and provide the data between the second processor and the stream processor at the second latency. The concept of memory of different tiers/locations having different access latencies is not novel, see Hutsell et al. (US 7,664,907), Singh et al. (US 7,836,229), Wegener (US 2013/0262809), Corsi et al. (US 2020/0110639), Wegener (WO 2013/149045),with Wegener in particular identifying how latencies are different between memories that are in the same integrated circuit as a processor and memories that are not in the same integrated circuit as a processor, and Corsi in particular identifying different latencies in a multi-core system. However, none of the references found provide for two sub-processors within a single processor, where the two sub-processors interact with different elements at different latencies, let alone the specific memory registers of the second, separate processor as claimed. This leads to a determination of allowable subject matter. Examiner notes that claim 19 recites a slightly broader scope, as it does not recite the specific streaming processor/scheduling processor within the first processor seen in claims 1 and 12. However, no reference was found to provide the different latency configuration as discussed above, and as such the discussion above still applies to claim 19. The dependent claims are indicated to recite allowable subject matter for dependence on one of the independent claims above. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hutsell, Singh, Wegener, Corsi, Wegener, as cited above, Reghunath et al. (US 10,534,736), Cai et al. (US 2019/0034239), Polychroniou et al. (US 2019/0377683), disclose relating buffer sizes with memory latency, Kotra et al. (US 2022/0100665) discloses moving data between registers and memory, but does not disclose the registers as being found in a separate processor from a control/operative core. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON D HO whose telephone number is (469)295-9093. The examiner can normally be reached Mon-Fri 8:00-4:00 CT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.D.H./Examiner, Art Unit 2139 /REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
Read full office action

Prosecution Timeline

Jul 31, 2024
Application Filed
Apr 02, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12578886
METHOD AND APPARATUS FOR MEMORY MANAGEMENT IN MEMORY DISAGGREGATION ENVIRONMENT
2y 5m to grant Granted Mar 17, 2026
Patent 12572356
MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING
2y 5m to grant Granted Mar 10, 2026
Patent 12561252
DYNAMIC CACHE LOADING AND VERIFICATION
2y 5m to grant Granted Feb 24, 2026
Patent 12554418
MEMORY CHANNEL CONTROLLER OPERATION BASED ON DATA TYPES
2y 5m to grant Granted Feb 17, 2026
Patent 12524340
ARRAY ACCESS WITH RECEIVER MASKING
2y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
90%
With Interview (+15.1%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 251 resolved cases by this examiner. Grant probability derived from career allow rate.

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