Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/3/2025 is being considered by the examiner.
Claim Objections
Claims 11-20 are objected to because of the following informalities:
In claim 11, line 3, “DMA” should read -direct memory access (DMA)-;
In claim 20, line 2, “DMA” should read -direct memory access (DMA)-.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “associated” in claim 1 is a relative term which renders the claim indefinite. The term “associated” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Similar problems exist in claims 2-6, 8, 11-16, 18, and 20.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (U.S. Publication No. 2023/0153266 A1), hereafter referred to as Hung’266.
Referring to claim 1, Hung’266 as claimed, a system comprising: one or more processors (processor, see para. [0281] and Fig. 10H) to: obtain, using a direct memory access (DMA) system (DMA system including a hardware sequencer, see para. [0281]), data representing a frame format comprising a set of DMA transfers to be performed in a sequence according to a frame type (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see para. [0286]), the frame format including a set of descriptor identifiers corresponding to descriptors (the descriptor SRAM include one or more descriptors which define tile dimensions (e.g. a tile width, dx, and a tile height dy), a starting point for the image or frame, and/or other micro information about the scan type of the descriptor, see paras. [0285], [0287]); determine, using the DMA system, the frame type of the frame format from a set of frame types based at least on the frame format (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286]-[0288]); obtain, using the DMA system, data associated with the descriptors based at least on the descriptor identifiers of the frame format and the frame type of the frame format (descriptors that defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286], [0290], [0291]); and cause, using the DMA system, the set of DMA transfers to be performed in accordance with the sequence between a source memory to a destination memory based at least on the frame format and the descriptors (moving data from a source to a destination such as from memory to VMEM, see para. [0275]), wherein the DMA system is configured to process frame formats associated with each frame type of the set of frame types (frame format and processing, see paras. [0291]-[0298]).
As to claim 2, Hung’266 also discloses the frame format is associated with a frame addressing frame format (frame format include frame headers for header control, offset control, and padding control, and include column headers and/or row headers for column or rows of the frame (e.g. column headers for vertical scan patterns and row headers for raster scan patterns, see para. [0286]; the register control aid in controlling a traversal order, prefetching, and/or other frame addressing controls, see para. [0288]), and wherein the one or more processors are to: configure, using the DMA system, the set of DMA transfers to be performed based at least on the frame addressing frame format indicating that the set of DMA transfers are to be performed in accordance with a raster scan sequence, wherein the raster scan sequence is associated with at least one traversal order from among a plurality of traversal orders (raster scan patterns, see para. [0286]; traversal order is raster, see para. [0287]; frame format implemented for a raster scan sequence, a frame format in a raster mode with frame addressing processing, see para. [0291] and Figs. 10I-K).
As to claim 3, Hung’266 also discloses the frame format is associated with a descriptor addressing frame format (a number of descriptor rows and/or descriptor columns; managing address sequencing across descriptors/tiles, see paras. [0287]-[0294]), and wherein the one or more processors are to: cause, based at least on configuring the DMA system, the set of DMA transfers to be performed based at least on the descriptor addressing frame format indicating that the set of DMA transfers are to be performed based at least on a configuration of the DMA transfers by an accelerator (a processing controller such as an R5 processor, a CPU, an ARM processor, etc. use programmed code and/or setting from a higher level engine to program or configure the HW sequencer command SRAM and the descriptor SRAM, see para. [0284]; a programmable vision accelerator (PVA), see paras. [0302], [0380], [0381], [0383], [0384]).
As to claim 4, Hung’266 also discloses the frame format is associated with a random region addressing frame format (different data points or features for irregular or unknown data patters, see para. [0302]), and wherein the one or more processors are to: cause, using the DMA system, the set of DMA transfers to be performed based at least on the set of descriptors corresponding to regions of interest within a frame identified by the frame format (DMA to reconfigure its descriptors based on outputs of the processor…update descriptors of a DMA to track feature data including location, see paras. [0302]-[0305]).
As to claim 5, Hung’266 also discloses the one or more processors are to: determine the frame type based at least on the frame format, the frame type indicating that one or more byte fields of the frame format are reserved byte fields (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286], [0290], [0291]); and obtain the data associated with the descriptors based at least on the frame format type (the format may include, for each address/data pair, four bytes for the address and four bytes for the data, see para. [0309]; retrieve the proper data, see paras. [0309]-[0312]).
As to claim 6, Hung’266 also discloses the frame type includes: a descriptor addressing frame type associated with one or more updated descriptors (a number of descriptor rows and/or descriptor columns; managing address sequencing across descriptors/tiles, see paras. [0287]-[0294]) generated using an accelerator (a processing controller such as an R5 processor, a CPU, an ARM processor, etc. use programmed code and/or setting from a higher level engine to program or configure the HW sequencer command SRAM and the descriptor SRAM, see para. [0284]; a programmable vision accelerator (PVA), see paras. [0302], [0380], [0381], [0383], [0384]), or a random region frame type associated with one or more descriptors (different data points or features for irregular or unknown data patters, see para. [0302]) indicating at least one offset and at least one descriptor associated with a tile bounding a region of interest within a frame, the frame specified by the frame format (frame header offset control may include a frame tile offset (e.g., an offset from tile to tile) and a frame offset (e.g., an offset between two or more frames that may be read out using a single channel, see paras. [0286] and [0287]; also note: regions of interest, see paras. [0302]-[0305]).
As to claim 7, Hung’266 also discloses the one or more processors are to: cause the set of DMA transfers to be performed in a single channel based at least on the frame format type and the descriptors (using a single channel, see paras. [0286], [0291]).
As to claim 8, Hung’266 also discloses the frame format comprises one or more reserved byte fields (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286], [0290], [0291]); and wherein the one or more processors are to: obtain the data associated with the descriptors, the descriptors comprising one or more descriptor byte fields corresponding to one or more of the reserved byte fields of the frame format (the format may include, for each address/data pair, four bytes for the address and four bytes for the data, see para. [0309]; retrieve the proper data, see paras. [0309]-[0312]).
As to claim 9, Hung’266 also discloses the one or more processors are to: determine one or more aspects of the set of DMA transfers based at least on the frame type, and determine the sequence of the set of DMA transfers based at least on the one or more aspects of the set of DMA transfers (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, frame header offset, frame tile offset, frame offset, etc., see paras. [0286], [0290], [0291]; also note: moving data to memory, see paras. [0276]-[0279]).
As to claim 10, Hung’266 also discloses the one or more processors are comprised in at least one of: a control system for an autonomous or semi-autonomous machine (autonomous and semi-autonomous vehicles, see para. [0069] and Figs. 13A-D); a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations (simulations, see paras. [0391] and [0452]); a system for performing digital twin operations; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; a system for performing deep learning operations (deep learning applications, see paras. [0246], [0302], [0303]); a system for generating or presenting at least one of augmented reality content, virtual reality content, or mixed reality content (augmented reality, virtual reality, mixed reality, see paras. [0069], [0384]); a system for hosting one or more real-time streaming applications (real-time, see paras. [0099], [0225], [0391]); a system for implementing large language models (LLMs); a system for implementing vision language models (VLMs) (computer vision algorithms, see paras. [0207], [0230], [0246], [0321]); a system for implementing multi-modal language models (machine learning models, see para. [0452]); a system implemented using an edge device (edge servers/device, see paras. [0486]-[0488]); a system implemented using a robot (robots, see para. [0069]); a system for performing conversational AI operations; a system for performing generative Al operations (artificial intelligence, see paras. [0069], [0353], [0369]); a system for generating synthetic data; a system incorporating one or more virtual machines (VMs) (virtual machines, see para. [0457]); a system implemented at least partially in a data center (data center, see Fig. 15); or a system implemented at least partially using cloud computing resources (cloud, see paras. [0450], [0476], [0486], and [0487]).
Note claims 11 and 20 recite similar limitations of claim 1. Therefore, they are rejected based on the same reason accordingly.
Note claim 12 recites the corresponding limitations of claim 2. Therefore, it is rejected based on the same reason accordingly.
Note claim 13 recites the corresponding limitations of claim 3. Therefore, it is rejected based on the same reason accordingly.
Note claim 14 recites the corresponding limitations of claim 4. Therefore, it is rejected based on the same reason accordingly.
Note claim 15 recites the corresponding limitations of claim 5. Therefore, it is rejected based on the same reason accordingly.
Note claim 16 recites the corresponding limitations of claim 6. Therefore, it is rejected based on the same reason accordingly.
Note claim 17 recites the corresponding limitations of claim 7. Therefore, it is rejected based on the same reason accordingly.
Note claim 18 recites the corresponding limitations of claim 8. Therefore, it is rejected based on the same reason accordingly.
Note claim 19 recites the corresponding limitations of claim 9. Therefore, it is rejected based on the same reason accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
BOESCH et al. (U.S. Publication No. 2020/0272779 A1) discloses a hardware accelerator engine arranged to implement a portion of the deep convolutional neural network.
Liu et al. (U.S. Publication No. 2022/0114702 A1) discloses upsampling an image using one or more neural networks.
Hari et al. (U.S. Publication No. 2023/0079196 A1) discloses adversarial scenarios for safety testing of autonomous vehicles.
Hari et al. (U.S. Publication No. 2021/0387643 A1) discloses tensor-based driving scenario characterization.
BOESCH et al. (U.S. Publication No. 2018/0189641 A1) discloses a hardware accelerator engine that supports efficient mapping of convolutional stages of deep neural network algorithms.
Modukuri et al. (U.S. Publication No. 2021/0286752 A1) discloses techniques to transfer data among hardware devices.
Butterfield et al. (U.S. Patent No. 5,502,804) discloses a method for displaying a page with graphics information on a continuous synchronous raster output device.
Butterfield et al. (U.S. Patent No. 5,509,115) discloses an apparatus for displaying a page with graphics information on a continuous synchronous raster output device.
HUNG et al. (U.S. Publication No. 2016/0321074 A1) discloses configurable components in a programmable vision accelerator to facilitate loop collapsing.
Diril et al. (U.S. Publication No. 2019/0171927 A1) discloses layer-level quantization in neural networks.
Donnelly (U.S. Publication No. 2022/0044109 A1) discloses quantization-aware training of quantized neural networks.
Hung et al. (U.S. Publication No. 2023/0046642 A1) discloses hardware accelerated anomaly detection in a system on a chip.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TITUS WONG whose telephone number is (571)270-1627. The examiner can normally be reached Monday-Friday, 10am-6pm.
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/TITUS WONG/Primary Examiner, Art Unit 2181
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