Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The amendment filed on July 22, 2026 has been received and entered.
Applicant’s Amendments to the Claims have been received and acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (U.S. Publication No. 2023/0153266 A1), hereafter referred to as Hung’266 in view of BROWN et al. (U.S. Publication No. 2018/0150542 A1), hereafter referred to as BROWN’542.
Referring to claim 1, Hung’266 as claimed, a system comprising: one or more processors (processor, see para. [0281] and Fig. 10H) to: obtain, using a direct memory access (DMA) system (DMA system including a hardware sequencer, see para. [0281]), data representing a frame format comprising a set of DMA transfers to be performed in a sequence according to a frame type (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see para. [0286]), the frame format including a set of descriptor identifiers corresponding to descriptors (the descriptor SRAM include one or more descriptors which define tile dimensions (e.g. a tile width, dx, and a tile height dy), a starting point for the image or frame, and/or other micro information about the scan type of the descriptor, see paras. [0285], [0287]); determine, using the DMA system, and based at least on the frame format the frame type (frame format and processing, see paras. [0291]-[0298]), the DMA system being configured to process frame format corresponding to a frame type (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286]-[0288]); obtain, using the DMA system, data corresponding to the descriptors based at least on the descriptor identifiers of the frame format and the frame type of the frame format (descriptors that defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286], [0290], [0291]); and cause, using the DMA system, the set of DMA transfers to be performed in accordance with the sequence between a source memory to a destination memory based at least on the frame format and the descriptors (moving data from a source to a destination such as from memory to VMEM, see para. [0275]).
However, Hung’266 does not appear to teach identifying format/type from multiple types and processing the data corresponding to identified format/type.
BROWN’542 discloses identifying format/type from multiple types and processing the data corresponding to identified format/type (the descriptor contains a descriptor type field; there are at least three types of descriptors, which are data descriptors, control descriptors, auxiliary descriptors; the descriptor channel block decodes the descriptor and determines its type; the system processes the descriptor based on the determined type, see paras. [0063]-[0068], [0071]-[0076], [0086], [0106]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Hung’266’s invention to comprise identifying format/type from multiple types and processing the data corresponding to identified format/type, as taught by BROWN’542, in order to provide for hardware accelerated data movement between memories (see para. [0039]).
As to claim 2, Hung’266 also discloses the frame format is associated with a frame addressing frame format (frame format include frame headers for header control, offset control, and padding control, and include column headers and/or row headers for column or rows of the frame (e.g. column headers for vertical scan patterns and row headers for raster scan patterns, see para. [0286]; the register control aid in controlling a traversal order, prefetching, and/or other frame addressing controls, see para. [0288]), and wherein the one or more processors are to: configure, using the DMA system, the set of DMA transfers to be performed based at least on the frame addressing frame format indicating that the set of DMA transfers are to be performed in accordance with a raster scan sequence, wherein the raster scan sequence corresponds to at least one traversal order from among a plurality of traversal orders (raster scan patterns, see para. [0286]; traversal order is raster, see para. [0287]; frame format implemented for a raster scan sequence, a frame format in a raster mode with frame addressing processing, see para. [0291] and Figs. 10I-K).
As to claim 3, Hung’266 also discloses the frame format corresponds to a descriptor addressing frame format (a number of descriptor rows and/or descriptor columns; managing address sequencing across descriptors/tiles, see paras. [0287]-[0294]), and wherein the one or more processors are to: cause, based at least on configuring the DMA system, the set of DMA transfers to be performed based at least on the descriptor addressing frame format indicating that the set of DMA transfers are to be performed based at least on a configuration of the DMA transfers by an accelerator (a processing controller such as an R5 processor, a CPU, an ARM processor, etc. use programmed code and/or setting from a higher level engine to program or configure the HW sequencer command SRAM and the descriptor SRAM, see para. [0284]; a programmable vision accelerator (PVA), see paras. [0302], [0380], [0381], [0383], [0384]).
As to claim 4, Hung’266 also discloses the frame format corresponds to a random region addressing frame format (different data points or features for irregular or unknown data patterns, see para. [0302]), and wherein the one or more processors are to: cause, using the DMA system, the set of DMA transfers to be performed based at least on the set of descriptors corresponding to regions of interest within a frame identified by the frame format (DMA to reconfigure its descriptors based on outputs of the processor…update descriptors of a DMA to track feature data including location, see paras. [0302]-[0305]).
As to claim 5, Hung’266 also discloses the one or more processors are to: determine the frame type based at least on the frame format, the frame type indicating that one or more byte fields of the frame format are reserved byte fields (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286], [0290], [0291]); and obtain the data corresponding to the descriptors based at least on the frame format type (the format may include, for each address/data pair, four bytes for the address and four bytes for the data, see para. [0309]; retrieve the proper data, see paras. [0309]-[0312]).
As to claim 6, Hung’266 also discloses the frame type includes: a descriptor addressing frame type corresponding to one or more updated descriptors (a number of descriptor rows and/or descriptor columns; managing address sequencing across descriptors/tiles, see paras. [0287]-[0294]) generated using an accelerator (a processing controller such as an R5 processor, a CPU, an ARM processor, etc. use programmed code and/or setting from a higher level engine to program or configure the HW sequencer command SRAM and the descriptor SRAM, see para. [0284]; a programmable vision accelerator (PVA), see paras. [0302], [0380], [0381], [0383], [0384]), or a random region frame type corresponding to one or more descriptors (different data points or features for irregular or unknown data patterns, see para. [0302]) indicating at least one offset and at least one descriptor corresponding to a tile bounding a region of interest within a frame, the frame specified by the frame format (frame header offset control may include a frame tile offset (e.g., an offset from tile to tile) and a frame offset (e.g., an offset between two or more frames that may be read out using a single channel, see paras. [0286] and [0287]; also note: regions of interest, see paras. [0302]-[0305]).
As to claim 7, Hung’266 also discloses the one or more processors are to: cause the set of DMA transfers to be performed in a single channel based at least on the frame format type and the descriptors (using a single channel, see paras. [0286], [0291]).
As to claim 8, Hung’266 also discloses the frame format comprises one or more reserved byte fields (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, etc., see paras. [0286], [0290], [0291]); and wherein the one or more processors are to: obtain the data corresponding to the descriptors, the descriptors comprising one or more descriptor byte fields corresponding to one or more of the reserved byte fields of the frame format (the format may include, for each address/data pair, four bytes for the address and four bytes for the data, see para. [0309]; retrieve the proper data, see paras. [0309]-[0312]).
As to claim 9, Hung’266 also discloses the one or more processors are to: determine one or more aspects of the set of DMA transfers based at least on the frame type, and determine the sequence of the set of DMA transfers based at least on the one or more aspects of the set of DMA transfers (frame format describes frames at a higher level by processing tile rows/columns, see para. [0283]; frame format defines the frame as a whole, the size of the frame, the frame padding, frame header offset, frame tile offset, frame offset, etc., see paras. [0286], [0290], [0291]; also note: moving data to memory, see paras. [0276]-[0279]).
As to claim 10, Hung’266 also discloses the one or more processors are comprised in at least one of: a control system for an autonomous or semi-autonomous machine (autonomous and semi-autonomous vehicles, see para. [0069] and Figs. 13A-D); a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations (simulations, see paras. [0391] and [0452]); a system for performing digital twin operations; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; a system for performing deep learning operations (deep learning applications, see paras. [0246], [0302], [0303]); a system for generating or presenting at least one of augmented reality content, virtual reality content, or mixed reality content (augmented reality, virtual reality, mixed reality, see paras. [0069], [0384]); a system for hosting one or more real-time streaming applications (real-time, see paras. [0099], [0225], [0391]); a system for implementing large language models (LLMs); a system for implementing vision language models (VLMs) (computer vision algorithms, see paras. [0207], [0230], [0246], [0321]); a system for implementing multi-modal language models (machine learning models, see para. [0452]); a system implemented using an edge device (edge servers/device, see paras. [0486]-[0488]); a system implemented using a robot (robots, see para. [0069]); a system for performing conversational AI operations; a system for performing generative Al operations (artificial intelligence, see paras. [0069], [0353], [0369]); a system for generating synthetic data; a system incorporating one or more virtual machines (VMs) (virtual machines, see para. [0457]); a system implemented at least partially in a data center (data center, see Fig. 15); or a system implemented at least partially using cloud computing resources (cloud, see paras. [0450], [0476], [0486], and [0487]).
Note claims 11 and 20 recite similar limitations of claim 1. Therefore, they are rejected based on the same reason accordingly.
Note claim 12 recites the corresponding limitations of claim 2. Therefore, it is rejected based on the same reason accordingly.
Note claim 13 recites the corresponding limitations of claim 3. Therefore, it is rejected based on the same reason accordingly.
Note claim 14 recites the corresponding limitations of claim 4. Therefore, it is rejected based on the same reason accordingly.
Note claim 15 recites the corresponding limitations of claim 5. Therefore, it is rejected based on the same reason accordingly.
Note claim 16 recites the corresponding limitations of claim 6. Therefore, it is rejected based on the same reason accordingly.
Note claim 17 recites the corresponding limitations of claim 7. Therefore, it is rejected based on the same reason accordingly.
Note claim 18 recites the corresponding limitations of claim 8. Therefore, it is rejected based on the same reason accordingly.
Note claim 19 recites the corresponding limitations of claim 9. Therefore, it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 7/22/2026 have been fully considered but they are moot due to new grounds of rejection.
In summary, Hung’266 and BROWN’542 disclose the claimed limitations as set forth.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TITUS WONG whose telephone number is (571)270-1627. The examiner can normally be reached Monday-Friday, 10am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TITUS WONG/Primary Examiner, Art Unit 2181
Prosecution Insights