DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/17/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2018/0026029 and Lin hereinafter) in view of Yamamoto (US 20220209769 A1).
Regarding claim 1, Lin discloses a circuit [fig. 1] comprising: a transistor [108]; a depletion mode device [102, par. 0016] comprising a control gate [G] and a source [S] directly connected to an end of a resistor divider [end of resistor 106/ divisional 114]; and a first resistor [122] connected directly between a predetermined voltage (voltage at 124) and directly connected to the control gate of the depletion mode device [102], wherein: the transistor [S/D 108] is directly connected to the first resistor [122] and the control gate of the depletion mode device [gate 102]; and wherein when the transistor is OFF [108 off], the control gate of the depletion mode device is pulled up by the first resistor to the predetermined voltage fed into the control gate [para. 0014-0019]. Lin does not explicitly disclose a resistor divider.
However, Yamamoto discloses [see fig. 1] a depletion-type NMOS transistor [D1] source [SD1] directly connected to an end of a resistor divider [R1/R2]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin by incorporating the resistor divider as taught in Yamamoto, because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent voltage divider which provide constant voltage circuit that supplies a constant voltage [par. 0030].
Regarding claim 10, Lin discloses a circuit [fig. 1] comprising: a transistor [108] directly connected to a control gate integrated with a depletion mode device [gate 102, par. 0016], which is pulled to ground when an output of the transistor is high and pulled to a predetermined voltage (voltage at 124) when the output of the transistor is low; and a resistor [122] connected between the predetermined voltage (voltage at 124) and directly to a control body of the control gate [G], the predetermined voltage (voltage at 124) being fed into the control body through the resistor to pull the control gate high, wherein a source [S] of the depletion mode device is directly connected to an end of a resistor divider [end of resistor 106/divisional 114] and the transistor [108 S/D] is directly connected to the resistor [122]. Lin does not explicitly disclose a resistor divider.
However, Yamamoto discloses [see fig. 1] a depletion-type NMOS transistor [D1] source [SD1] directly connected to an end of a resistor divider [R1/R2]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin by incorporating the resistor divider as taught Yamamoto, because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent voltage divider which provide constant voltage circuit that supplies a constant voltage [par. 0030].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto further in view of Udrea et al. (US 11658236 and Udrea hereinafter).
Regarding claim 2, Lin in view of Yamamoto teaches all the features with respect to claim 1 as outlined above. Lin in view of Yamamoto further discloses the control gate depletion transistor [102, fig. 1] and a second end of the resistor [R2, fig. 1, ref. Yamamoto] device is directly connected to ground [GND]. Lin in view of Yamamoto does not explicitly disclose PGaN gate,
However, Udrea discloses [see fig. 13 and cl. 20, In 66] a PGaN depletion mode device [36]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto by incorporating the PGaN depletion mode transistor because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent transistor device.
Claims 3, 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto further in view of Shina (US 2022/0057825).
Regarding claim 3, Lin in view of Yamamoto teaches all the features with respect to claim 1 as outlined above. Lin in view of Yamamoto does not explicitly disclose a comparator with its output connected to the transistor and resistor divider comprising a resistor that provides a fixed reference voltage to the input of the comparator, wherein the comparator comprises a first input connected to the resistor divider and a second input connected to a moving voltage.
However, Shina discloses [fig. 1] a comparator [33] with its output connected to a transistor [31] wherein a resistor divider [divider 15/13] that provides a fixed reference voltage [voltage between 15 and 13] to the input of the comparator, wherein the comparator comprises a first input [(-) input terminal] connected to the resistor divider and a second input [(+) input terminal] connected to a moving voltage [voltage between 16 and 12]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Li in view of Yamamoto by incorporating a resistor divider as taught in Shina in order to utilize well known voltage divider.
Regarding claim 7, Lin in view of Yamamoto further in view of Shina teaches wherein an input of the transistor [31] is directly from an output of the comparator [output of 33].
Regarding claim 17, Lin in view of Yamamoto teaches all the features with respect to claim 10 as outlined above. Lin in view of Yamamoto does not explicitly disclose a resistor of the resistor divider between the output of the control gate and an input to a comparator.
However, Shina discloses [fig. 1] a resistor [15] of a resistor divider [divider 15/13] between an output of the control gate [gate 32] and an input to a comparator [33]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto by incorporating a resistor divider as taught in Shina in order to utilize well known voltage divider.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto further in view of Lin494 et al.
Regarding claim 11, Lin in view of Yamamoto teaches all the features with respect to claim 10 as outlined above. Lin in view of Yamamoto further discloses wherein the transistor controls a pinch-off voltage of the control gate and a second end of the resistor device [R2] is directly connected to ground. Lin in view of Yamamoto does not explicitly disclose a first clamp positioned between the control gate and a comparator and a second clamp connected between ground and another input of the comparator. and.
However, Lin494 discloses [fig. 1] a clamp [C1] connected to a comparator [120] and another clamp [C2] connected to another input of the comparator. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto by incorporating a clamp so that a clamp positioned between the resistor and the comparator [COMP of XU] and connected between ground as taught in Lin494 in order to improve performance of the circuit.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto and Lin494 et al. further in view of Shina.
Regarding claim 12, Lin in view of Yamamoto in view of Lin494 teaches wherein the transistor [31, fig. 1] receives its input directly from an output of the comparator [output 33]. Lin in view of Yamamoto in view of Lin494 teaches does not explicitly disclose wherein the comparator comprises a first input connected to the resistor divider and a second input connected to a moving voltage.
However, Shina discloses [fig. 1] wherein a comparator [33] comprises a first input [(-) input terminal] connected to a resistor divider [13/15] and a second input [(+) input terminal] connected to a moving voltage [voltage between 16 and 12]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Li in view of Yamamoto in view of Lin494 by incorporating a resistor divider as taught in Shina in order to utilize well known voltage divider.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto and Shina further in view of Yasusaka (US 2021/0067149).
Regarding claim 5, Lin in view of Yamamoto and Shina teaches all the features with respect to claim 3 as outlined above. Lin in view of Yamamoto and Shina does not explicitly disclose further comprising a plurality of inverters in series with an output of the comparator.
However, Yasusaka discloses [see fig. 1] a plurality of inverters [INVa, INVb] in series with an output of the comparator [CMP]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto and Shina by incorporating the inverters as taught in Yasusaka in order to improve the circuit.
Regarding claim 6, Lin in view of Yamamoto and Shina teaches all the features with respect to claim 3 as outlined above. Lin in view of Yamamoto and Shina does not explicitly disclose wherein an input of the transistor is an output of an inverter connected to the comparator in series and the output of the depletion mode device.
However, Yasusaka discloses [see fig. 1] wherein an input of the transistor [Tr11] is an output of an inverter [IN Va] connected to the comparator in series. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto and Shina by incorporating the feedback as taught in Yasusaka in order to improve performance in the circuit.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto and Lin494 et al. further in view of Yasusaka.
Regarding claim 13, Lin in view of Yamamoto further in view of Lin494 teaches all the features with respect to claim 11 as outlined above. Lin in view of Yamamoto further in view of Lin494 does not explicitly disclose further comprising a plurality of inverters in series with an output of the comparator.
However, Yasusaka discloses [see fig. 1] a plurality of inverters [INVa, INVb] in series with an output of the comparator [CMP]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto further in view of Lin494 by incorporating the inverters as taught in Yasusaka in order to improve the circuit.
Regarding claim 14, Lin in view of Yamamoto further in view of Lin494 and Yasusaka teaches further comprising a resistor [13] in series with an input of the comparator [input 33].
Regarding claim 15, Lin in view of Yamamoto further in view of Lin494 teaches all the features with respect to claim 11 as outlined above. Lin in view of Yamamoto further in view of Lin494 further discloses wherein the transistor receives its input directly from an output of a first inverter of the plurality of inverters connected in series with the output of a comparator.
However, Yasusaka discloses [see fig. 1] the transistor receives its input directly from an output of a first inverter of a plurality of inverters [INVa, INVb] in series with a comparator [CMP]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto further in view of Lin494 by incorporating the inverters as taught in Yasusaka in order to improve the circuit.
Regarding claim 16, Lin in view of Yamamoto further in view of Lin494 and Yasusaka wherein the input to the comparator comprises an output of a second inverter [INVb, fig. 5 of Yasusaka] of the plurality of inverters connected in series with the output of the comparator.
Response to Arguments
The rejections of claims 1, 10 and 18 under nonstatutory double patenting over claims of US Patent No. 12,107,585 has been withdrawn.
Applicant’s amendments to the claims 1, 10 and 18 filed on 04/03/2026 has been entered and overcomes the applied obviousness double patenting rejection over claims of US Patent No.12, 107, 585. Therefore, the rejection has been withdrawn.
Applicant's arguments filed on 04/03/2026 , with respect to the rejection of claims 1 and 10 have been fully considered but they are not persuasive.
Regarding claim 1, applicant argues that Lin in view of Yamamoto teaches fails to disclose " the transistor is directly connected to the first resistor and the control gate of the depletion mode device". Examiner respectfully disagrees.
However, Lin discloses as shown in figure 1, the transistor [S/D 108] is directly connected to the first resistor [122] and the control gate of the depletion mode device [gate 102].
Regarding claim 10, applicant argues that Lin in view of Yamamoto teaches fails to disclose “a transistor directly connected to a control gate integrated with a depletion mode device and the transistor is directly connected to the resistor”. Examiner respectfully disagrees.
However, Lin discloses as shown in figure 1, a transistor [108] directly connected to a control gate integrated with a depletion mode device [gate 102, par. 0016] and the transistor [108 S/D] is directly connected to the resistor [122].
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 4 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, Lin in view of Yamamoto does not disclose or fairly suggest “another clamp positioned between ground and the second input of the comparator.”
Regarding claim 8, Lin in view of Yamamoto does not disclose or fairly suggest “the clamp is positioned between the resistor and the first input of the comparator”
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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