DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 10 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11 and 19 of U.S. Patent No. 12,107,585 . Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of the instant application is broader than claim 1 of the Patent US 12,107,585 (without the claim limitation “a comparator; a transistor connected to an output of the comparator, a depletion mode device connected to ground and a first reference voltage (Vdd), and comprising a control gate directly connected to an output of the transistor and to an input of the comparator, the output of the transistor controlling a pinch-off voltage at the control gate of the depletion mode device”). And the instant application further recites “a depletion mode device comprising a control gate and a source directly connected to an end of a resistor divider”.
Although the wording differs, the claims are not patentably distinct. The patent teaches a depletion mode device connected between ground and a reference voltage, with its control gate directly connected to the output of a transistor and to the input of a comparator.
The instant application claim similarly recites a depletion mode device comprising a control gate and a source directly connected to an end of a resistor divider. Connecting the depletion mode device to a resistor divider end is an obvious design choice for establishing a reference point and would have been an obvious variation of connecting the device between ground and a reference voltage as taught in the patent claim. Therefore, claim 1 is found obvious and not patentably distinct from the claim 1 of the Patent US 12,107, 585.
Claim 10 of the instant application is broader than claim 11 of the Patent US 12,107,585 (without the claim limitation “a comparator which compares a fixed, reference voltage to a moving voltage; a transistor which is controlled by an output of the comparator; wherein the control gate is connected directly to an output of the transistor and an input of the comparator”). And the instant application further recites “a depletion mode device comprising a control gate and a source directly connected to an end of a resistor divider”. Although the wording differs, the claims are not patentably distinct. The patent teaches a depletion mode device connected between ground and a reference voltage, with its control gate directly connected to the output of a transistor and to the input of a comparator.
The instant application claim similarly recites a depletion mode device comprising a control gate and a source directly connected to an end of a resistor divider. Connecting the depletion mode device to a resistor divider end is an obvious design choice for establishing a reference point and would have been an obvious variation of connecting the device between ground and a reference voltage as taught in the patent claim. Therefore, claim 10 is found obvious and not patentably distinct from the claim 11 of the Patent US 12,107, 585.
Claim 18 of the instant application is broader than claim 19 of the Patent US 12,107,585 (without the claim limitation “by using an output of a comparator, and feeding a moving voltage (Vin) and a fixed, reference voltage (Vdd) passing through the control gate of the depletion mode device, into respective inputs of the comparator.”).
The instant application further recites “wherein a source of the depletion mode device is directly connected to an end of a resistor divider, and the transistor is directly connected to the resistor.”. The patented claim teaches the same functional relationship (i.e., grounding the control gate of depletion mode device when the transistor is on). The instant application claim adds additional structural limitations relate to the biasing (source connected to a resistor divider node and the transistor directly connected to the resistor). These additional features merely specify one predictable implementation of the same control gate grounding behavior already required by the patented claim.
Connecting the source to a resistor divider node and connecting the transistor directly to the resistor are well known circuit variation that do not alter the operation of grounding the control gate during the transistor conduction. Thus, the instant claim represent an obvious modification of the patented claim and does not define a patentably distinct invention. Therefore, claim 18 is found obvious and not patentably distinct from the claim 19 of the Patent US 12, 107, 585. As shown in the table below, the remainder of the claim language is identical between the patented claims and the instant application claims.
Instant application App 18/790021
US Patent No. 12,107,585
1. A circuit comprising: a transistor; a depletion mode device comprising a control gate and a source directly connected to an end of a resistor divider; and
a first resistor connected directly between a
predetermined voltage (Vddl) and directly
connected to the control gate of the depletion
mode device, wherein when the transistor is
OFF, the control gate of the depletion mode
device is pulled up by the first resistor to the
predetermined voltage (Vddl) fed into the
control gate.
1. A circuit comprising: a comparator; a transistor connected to an output of the comparator; a depletion mode device connected to ground and a first reference voltage (Vdd), and comprising a control gate directly connected to an output of the transistor and to an input of the comparator, the output of the transistor controlling a pinch-off voltage at the control gate of the depletion mode device; and a first resistor connected directly between a predetermined voltage (Vdd1) and directly connected to the control gate of the depletion mode device, wherein when the transistor is OFF, the control gate body of the depletion mode device is pulled up by the resistor to the predetermined voltage (Vdd1) fed into the control gate.
10. A circuit comprising: a transistor a control gate integrated with a depletion mode device, which is pulled to ground when an output of the transistor is high and pulled to a predetermined voltage (Vdd1) when the output of the transistor is low;
and a resistor connected between the predetermined voltage (Vdd1) and directly to a control body of the control gate, the predetermined voltage (Vdd1) being fed into the control body through the resistor to pull the control gate high, wherein a source of the depletion mode device is directly connected to an end of a resistor divider.
11. A circuit comprising: a comparator which compares a fixed, reference voltage to a moving voltage; a transistor which is controlled by an output of the comparator; a control gate integrated with a depletion mode device, which is pulled to ground when an output of the transistor is high and pulled to a predetermined voltage (Vdd1) when the output of the transistor is low, wherein the control gate is connected directly to an output of the transistor and an input of the comparator; and a resistor connected between the predetermined voltage (Vdd1) and directly to a control body of the control gate, the predetermined voltage (Vdd1) being fed into the control body through the resistor to pull the control gate high.
18. A method of operation comprising: controlling an ON state and OFF state of a transistor; bringing a control gate of a depletion mode device to ground when the transistor is in the ON state; and pulling a control to a first voltage (Vdd1) through a resistor connecting directly to the control gate when the transistor is in the OFF state, wherein a source of the depletion mode device is directly connected to an end of a resistor divider, and the transistor is directly connected to the resistor.
20. The method of claim 18, further comprising feeding a moving voltage (Vin) and a fixed, reference voltage (Vdd) passing through the control gate of the depletion mode device, into inputs of a comparator.
19. A method of operation comprising: controlling an ON state and OFF state of a transistor by using an output of a comparator; bringing a control gate of a depletion mode device to ground when the transistor is in the ON state; pulling a control to a first voltage (Vdd1) through a resistor connecting directly to the control gate when the transistor is in the OFF state; and feeding a moving voltage (Vin) and a fixed, reference voltage (Vdd) passing through the control gate of the depletion mode device, into respective inputs of the comparator.
Claims 2-9, 11-15 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-5, 7-16 and 20 of U.S. Patent No. 12,107,585.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “when the transistor is OFF, the control gate of the depletion mode device is pulled up by the first resistor to the predetermined voltage (Vddl) fed into the control gate”. It is unclear how the transistor being OFF relate to the control gate of the depletion mode device to be pulled up by the first resistor. Since the transistor does not have any structural connection with the depletion mode device and the resistor. Without reciting how the first resistor is electrically coupled to the control gate or how the transistor interact with the node, it is unclear how the claimed pull up action occurs. The claim therefore fails to provide the structural context necessary for a person of the ordinary skill in the art to understand the scope of the invention with reasonable certainty.
Claim 10 recites “a transistor a control gate integrated with a depletion mode device, which is pulled to ground when an output of the transistor is high and pulled to a predetermined voltage (Vdd1) when the output of the transistor is low”. It is unclear how a transistor and a control gate integrated with a depletion mode device are connected. The transistor does not have any structural connection with the depletion device and the rest of the circuit. The claim therefore fails to provide the structural context necessary for a person of the ordinary skill in the art to understand the scope of the invention with reasonable certainty.
Claim 18 recites “controlling an ON state and OFF state of a transistor; bringing a control gate of a depletion mode device to ground when the transistor is in the ON state; and pulling a control to a first voltage (Vdd1) through a resistor connecting directly to the control gate when the transistor is in the OFF state.”. The transistor does not have any structural connection with the depletion mode device and the resistor. The claim therefore fails to provide the structural context necessary for a person of the ordinary skill in the art to understand the scope of the invention with reasonable certainty.
Claims 2-9, 11-17 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claims 1, 10 and 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2018/0026029 and Lin hereinafter) in view of Yamamoto (US 20220209769 A1).
Regarding claim 1, Lin discloses a circuit [fig. 1] comprising: a transistor [108]; a depletion mode device [102, par. 0016] comprising a control gate [G] and a source [S] directly connected to an end of a resistor divider [end of resistor 106/ divisional 114]; and a first resistor [122] connected directly between a predetermined voltage (voltage at 124) and directly connected to the control gate of the depletion mode device, wherein when the transistor is OFF [108 off], the control gate of the depletion mode device is pulled up by the first resistor to the predetermined voltage fed into the control gate [para. 0014-0019]. Lin does not explicitly disclose a resistor divider.
However, Yamamoto discloses [see fig. 1] a depletion-type NMOS transistor [D1] source [SD1] directly connected to an end of a resistor divider [R1/R2]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin by incorporating the resistor divider as taught in Yamamoto, because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent voltage divider which provide constant voltage circuit that supplies a constant voltage [par. 0030].
Regarding claim 10, Lin discloses a circuit [fig. 1] comprising: a transistor [108] a control gate integrated with a depletion mode device [102, par. 0016], which is pulled to ground when an output of the transistor is high and pulled to a predetermined voltage (voltage at 124) when the output of the transistor is low; and a resistor [122] connected between the predetermined voltage (voltage at 124) and directly to a control body of the control gate [G], the predetermined voltage (voltage at 124) being fed into the control body through the resistor to pull the control gate high, wherein a source [S] of the depletion mode device is directly connected to an end of a resistor divider [end of resistor 106/divisional 114]. Lin does not explicitly disclose a resistor divider.
However, Yamamoto discloses [see fig. 1] a depletion-type NMOS transistor [D1] source [SD1] directly connected to an end of a resistor divider [R1/R2]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin by incorporating the resistor divider as taught Yamamoto, because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent voltage divider which provide constant voltage circuit that supplies a constant voltage [par. 0030].
Regarding claim 18, Lin discloses a method of operation [fig. 1] comprising: controlling an ON state and OFF state of a transistor [108]; bringing a control gate of a depletion mode [102] device to ground when the transistor is in the ON state; and pulling a control to a first voltage (voltage at 124) through a resistor [122] connecting directly to the control gate when the transistor is in the OFF state, wherein a source [S] of the depletion mode device is directly connected to an end of a resistor divider [end of resistor 106/divisional 114], and the transistor [108] is directly connected to the resistor [122]. Lin does not explicitly disclose a resistor divider.
However, Yamamoto discloses [see fig. 1] a depletion-type NMOS transistor [D1] source [SD1] directly connected to an end of a resistor divider [R1/R2]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin by incorporating the resistor divider as taught Yamamoto, because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent voltage divider which provide constant voltage circuit that supplies a constant voltage [par. 0030].
Regarding claim 19, Lin in view of Yamamoto discloses [fig. 1] wherein an output of the transistor [108] controls a pinch-off voltage of the depletion mode device, and a second end of the resistor device [end R2, fig. 1] is directly connected to ground [GND].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over XU et al. (CN 101582628B) in view of in view of Yamamoto.
Regarding claim 18. XU discloses a method of operation [fig. 5] comprising: controlling an ON state and OFF state of a transistor [Q5]; bringing a control gate [Q1] of a depletion mode device to ground when the transistor is in the ON state; pulling a control to a first voltage [VIN] through a resistor [R1] connecting directly to control gate when the transistor is in the OFF state, and the transistor [Q5] is directly connected to the resistor [R1]. Xu does not explicitly disclose wherein a source of the depletion mode device is directly connected to an end of a resistor divider.
However, Yamamoto discloses [see fig. 1] a depletion-type NMOS transistor [D1] source [SD1] directly connected to an end of a resistor divider [R1/R2]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin by incorporating the resistor divider as taught Yamamoto, because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent voltage divider which provide constant voltage circuit that supplies a constant voltage [par. 0030].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over XU et al. in view of in view of Yamamoto further in view of Shina (US 2022/0057825).
Regarding claim 20. XU in view of Yamamoto discloses further comprising feeding a moving voltage [voltage input to (+) of COMP] and a fixed, reference voltage [VT] passing through the control gate of the depletion mode device, into inputs of a comparator [output of COMP). XU in view of Yamamoto does not explicitly discloses wherein the comparator comprises a first input connected to the resistor divider and a second input connected to the moving voltage (Vin).
However, in the same field of endeavor, Shina discloses wherein a comparator [33] comprises a first input [(-) terminal] connected to a resistor divider [divider 15 and 13] and a second input [(+) terminal] connected to the moving voltage (Vin) [voltage between 16 and 12]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of XU in view of Yamamoto by incorporating the invention as taught in Shina in order provide a reference voltage circuit.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto further in view of Udrea et al. (US 11658236 and Udrea hereinafter).
Regarding claim 2, Lin in view of Yamamoto teaches all the features with respect to claim 1 as outlined above. Lin in view of Yamamoto further discloses the control gate depletion transistor [102, fig. 1] and a second end of the resistor [R2, fig. 1, ref. Yamamoto] device is directly connected to ground [GND]. Lin in view of Yamamoto does not explicitly disclose PGaN gate,
However, Udrea discloses [see fig. 13 and cl. 20, In 66] a PGaN depletion mode device [36]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto by incorporating the PGaN depletion mode transistor because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent transistor device.
Claims 3,7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto further in view of Shina (US 2022/0057825).
Regarding claim 3, Lin in view of Yamamoto teaches all the features with respect to claim 1 as outlined above. Lin in view of Yamamoto does not explicitly disclose a comparator with its output connected to the transistor and resistor divider comprising a resistor that provides a fixed reference voltage to the input of the comparator, wherein the comparator comprises a first input connected to the resistor divider and a second input connected to a moving voltage.
However, Shina discloses [fig. 1] a comparator [33] with its output connected to a transistor [31] wherein a resistor divider [divider 15/13] that provides a fixed reference voltage [voltage between 15 and 13] to the input of the comparator, wherein the comparator comprises a first input [(-) input terminal] connected to the resistor divider and a second input [(+) input terminal] connected to a moving voltage [voltage between 16 and 12]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Li in view of Yamamoto by incorporating a resistor divider as taught in Shina in order to utilize well known voltage divider.
Regarding claim 7, Lin in view of Yamamoto further in view of Shina teaches wherein an input of the transistor [31] is directly from an output of the comparator [output of 33].
Regarding claim 17, Lin in view of Yamamoto teaches all the features with respect to claim 10 as outlined above. Lin in view of Yamamoto does not explicitly disclose a resistor of the resistor divider between the output of the control gate and an input to a comparator.
However, Shina discloses [fig. 1] a resistor [15] of a resistor divider [divider 15/13] between an output of the control gate [gate 32] and an input to a comparator [33]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto by incorporating a resistor divider as taught in Shina in order to utilize well known voltage divider.
Claims 4 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto and Shina further in view of Lin et al. (US 2016/0072494 and Lin494 hereinafter)
Regarding claim 4, Lin in view of Yamamoto and Shina teaches all the features with respect to claim 3 as outlined above. Lin in view of Yamamoto and Shina further teaches wherein the transistor [P1, fig. 1] is directly connected to the first resistor [R2, fig. 1] and the control gate of the depletion mode device. Lin in view of Yamamoto and Shina does not explicitly disclose a clamp positioned between the resistor and the comparator and another clamp connected to another input of the comparator.
However, Lin494 discloses [fig. 1] a clamp [C1] connected to a comparator [120] and another clamp [C2] connected to another input of the comparator. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto and Shina by incorporating a clamp so that a clamp positioned between the resistor and the comparator [COMP of Shina] as taught in Lin494 in order to improve performance of the circuit.
Regarding claim 8, Lin in view of Yamamoto and Shina teaches all the features with respect to claim 3 as outlined above. Lin in view of Yamamoto and Shina does not explicitly wherein: the control gate is controlled by the output of the transistor; a clamp and another clamp comprise fixed pinch off depletion mode devices that protect the comparator from noise; and the clamp is positioned between the depletion mode device and the resistor and the another clamp is positioned between ground and the input of the comparator.
However, Lin494 discloses [fig. 1] wherein: the control gate is controlled by the output of the transistor; a clamp [C1] and another clamp comprise fixed pinch off depletion mode devices that protect the comparator from noise [par. 51]; and the clamp is positioned between the depletion mode device and the resistor and the another clamp is positioned between ground and the input of the comparator. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto and Shina by incorporating a clamp so that a clamp positioned between the resistor and the comparator [COMP of Shina] as taught in Lin494 in order to improve performance of the circuit.
Regarding claim 9, Lin in view of Yamamoto and Shina further in view of Lin494, wherein the control gate is pulled to ground when the transistor is high and pulled to the predetermined voltage (VIN) when the transistor is low.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto further in view of Lin494 et al.
Regarding claim 11, Lin in view of Yamamoto teaches all the features with respect to claim 10 as outlined above. Lin in view of Yamamoto further discloses wherein the transistor controls a pinch-off voltage of the control gate and a second end of the resistor device [R2] is directly connected to ground. Lin in view of Yamamoto does not explicitly disclose a first clamp positioned between the control gate and a comparator and a second clamp connected between ground and another input of the comparator. and.
However, Lin494 discloses [fig. 1] a clamp [C1] connected to a comparator [120] and another clamp [C2] connected to another input of the comparator. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto by incorporating a clamp so that a clamp positioned between the resistor and the comparator [COMP of XU] and connected between ground as taught in Lin494 in order to improve performance of the circuit.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto and Lin494 et al. further in view of Shina.
Regarding claim 12, Lin in view of Yamamoto in view of Lin494 teaches wherein the transistor [31, fig. 1] receives its input directly from an output of the comparator [output 33]. Lin in view of Yamamoto in view of Lin494 teaches does not explicitly disclose wherein the comparator comprises a first input connected to the resistor divider and a second input connected to a moving voltage.
However, Shina discloses [fig. 1] wherein a comparator [33] comprises a first input [(-) input terminal] connected to a resistor divider [13/15] and a second input [(+) input terminal] connected to a moving voltage [voltage between 16 and 12]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Li in view of Yamamoto in view of Lin494 by incorporating a resistor divider as taught in Shina in order to utilize well known voltage divider.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto and Shina further in view of Yasusaka (US 2021/0067149).
Regarding claim 5, Lin in view of Yamamoto and Shina teaches all the features with respect to claim 3 as outlined above. Lin in view of Yamamoto and Shina does not explicitly disclose further comprising a plurality of inverters in series with an output of the comparator.
However, Yasusaka discloses [see fig. 1] a plurality of inverters [INVa, INVb] in series with an output of the comparator [CMP]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto and Shina by incorporating the inverters as taught in Yasusaka in order to improve the circuit.
Regarding claim 6, Lin in view of Yamamoto and Shina teaches all the features with respect to claim 3 as outlined above. Lin in view of Yamamoto and Shina does not explicitly disclose wherein an input of the transistor is an output of an inverter connected to the comparator in series and the output of the depletion mode device.
However, Yasusaka discloses [see fig. 1] wherein an input of the transistor [Tr11] is an output of an inverter [IN Va] connected to the comparator in series. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto and Shina by incorporating the feedback as taught in Yasusaka in order to improve performance in the circuit.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Yamamoto and Lin494 et al. further in view of Yasusaka.
Regarding claim 13, Lin in view of Yamamoto further in view of Lin494 teaches all the features with respect to claim 11 as outlined above. Lin in view of Yamamoto further in view of Lin494 further discloses wherein the transistor is directly connected to the first resistor [R2] and the control gate of the depletion mode device. Lin in view of Yamamoto further in view of Lin494 does not explicitly disclose further comprising a plurality of inverters in series with an output of the comparator.
However, Yasusaka discloses [see fig. 1] a plurality of inverters [INVa, INVb] in series with an output of the comparator [CMP]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto further in view of Lin494 by incorporating the inverters as taught in Yasusaka in order to improve the circuit.
Regarding claim 14, Lin in view of Yamamoto further in view of Lin494 and Yasusaka teaches further comprising a resistor [13] in series with an input of the comparator [input 33].
Regarding claim 15, Lin in view of Yamamoto further in view of Lin494 teaches all the features with respect to claim 11 as outlined above. Lin in view of Yamamoto further in view of Lin494 further discloses wherein the transistor receives its input directly from an output of a first inverter of the plurality of inverters connected in series with the output of a comparator.
However, Yasusaka discloses [see fig. 1] the transistor receives its input directly from an output of a first inverter of a plurality of inverters [INVa, INVb] in series with a comparator [CMP]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Yamamoto further in view of Lin494 by incorporating the inverters as taught in Yasusaka in order to improve the circuit.
Regarding claim 16, Lin in view of Yamamoto further in view of Lin494 and Yasusaka wherein the input to the comparator comprises an output of a second inverter [INVb, fig. 5 of Yasusaka] of the plurality of inverters connected in series with the output of the comparator.
Response to Arguments
Applicant’s arguments with respect to claims filed on 11/22/2025 have been considered but are moot because the new ground of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842