Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 8, 12-13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masumura et al. (US Patent Pub 20230402443 A1) in view of Tanaka et al. (US Patent Pub 20210193380 A1).
Regarding Claim 1, Masumura teaches a semiconductor device comprising:
a first chip including a first semiconductor substrate, a first circuit formed at the first semiconductor substrate, and a first element insulating layer formed over the first semiconductor substrate (Masumura, fig. 13 teaches a first chip CPL including a first semiconductor substrate SB3, a first circuit MW3 formed at the first semiconductor substrate SB3, and a first element insulating layer PA3 formed over the first semiconductor substrate SB3);
a second chip disposed to be spaced apart from the first chip in a first direction and including a second semiconductor substrate, a second circuit formed at the second semiconductor substrate, and a second element insulating layer formed over the second semiconductor substrate (Fig. 13, second chip CPH spaced apart from the first chip CPL in a first direction and including a second semiconductor substrate SB2, a second circuit MW2 formed at the second semiconductor substrate SB2, and a second element insulating layer PA2 formed over the second semiconductor substrate SB2);
and a transformer chip provided separate from the first and second chip including a transformer, wherein the first circuit and the second circuit are configured to transmit signals or power via the transformer (Fig. 13, transformer chip CPC provided separate from CPL and CPH including a transformer (paragraph 0037 teaches the transformer is formed of L1a/L1b), wherein the first circuit and the second circuit are configured to transmit signals or power via the transformer (paragraph 0050)),
wherein the transformer chip (CPC) includes:
a third semiconductor substrate (fig. 13, third semiconductor substrate SB1);
and a third element insulating layer formed over the third semiconductor substrate, wherein the transformer is embedded in the third element insulating layer (fig. 13, third element insulating layer PA1 formed over the third semiconductor substrate SB1, wherein the transformer is embedded in the third element insulating layer (L1a is embedded in PA1)).
Masumura fails to teach a sub-mount chip provided separately from the first chip and the second chip, wherein the transformer chip is disposed over the sub-mount chip, and wherein the sub-mount chip includes a fourth semiconductor substrate and an insulating layer formed over the fourth semiconductor substrate.
However, Tanaka teaches a transformer chip disposed over a sub-mount chip, wherein the sub-mount chip includes a fourth semiconductor chip and an insulating layer formed over the fourth semiconductor chip (Tanaka, fig. 6, sub-mount chip (layers 26 and portion of 27 located below 20, see annotated figure below). The sub-mount chip includes a fourth semiconductor substrate 26, and an insulating layer 30 formed over 26).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Tanaka into the method of Masumura by forming the semiconductor device having a transformer chip disposed over a sub-mount chip, wherein the sub-mount chip includes a fourth semiconductor chip and an insulating layer formed over the fourth semiconductor chip. The ordinary artisan would have been motivated to modify Masumura in the manner set forth above for at least the purpose of enabling improvement of withstand voltage (Tanaka, paragraph 0005).
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Regarding Claim 2, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, wherein the third element insulating layer of the transformer chip includes a structure in which a first insulating film containing silicon nitride and a second insulating film containing silicon oxide are alternately stacked in plural (Tanaka, fig. 6 and paragraph 0096 teaches third element insulating layer (all structures including and above 20) includes first insulating film 29 which can be formed of silicon nitride, and a second insulating film 30 which contains silicon oxide stacked in plural).
Regarding Claim 3, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, wherein the insulating layer of the sub-mount chip includes a structure in which a first insulating film containing silicon nitride and a second insulating film containing silicon oxide are alternately stacked in plural (Tanaka, fig. 6 and paragraph 0096 teaches the insulating layer of the sub mount chip (layers 26 and portion of 27 located below 20) includes first insulating film 29 which can be formed of silicon nitride, and a second insulating film 30 which contains silicon oxide stacked in plural).
Regarding Claim 4, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, wherein the insulating layer of the sub-mount chip includes a structure in which an insulating film containing silicon oxide is stacked in plural (Tanaka, fig. 6 and paragraph 0096 teaches the insulating layer of the sub mount chip (layers 26 and portion of 27 located below 20) includes a second insulating film 30 which contains silicon oxide stacked in plural).
Regarding Claim 5, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, wherein a thickness of the sub-mount chip is smaller than a thickness of the transformer chip (Tanaka, fig. 6 teaches that the thickness of the sub-mount chip (layers 26 and portion of 27 located below 20) is smaller than a thickness of the transformer chip).
Regarding Claim 8, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, wherein a dimension of the sub-mount chip in the first direction is equal to a dimension of the transformer chip in the first direction (Tanaka, fig. 6 teaches a dimension of the sub-mount chip (layers 26 and portion of 27 located below 20) in the first direction is equal to a dimension of the transformer chip (portion of 6 including and above 20)).
Regarding Claim 12, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, wherein in a chip disposition state in which the transformer chip is disposed over the sub-mount chip, the third semiconductor substrate is interposed between the insulating layer of the sub-mount chip and the third element insulating layer of the transformer chip (Tanaka, Fig. 6 can be reinterpreted such that a chip disposition state in which the transformer chip (see annotated figure below) is disposed over the sub-mount chip (See annotated figure below), the third semiconductor substrate (30, see annotated figure below) is interposed between the insulating layer of the sub-mount chip (29/30 located within boundaries of sub-mount chip, see annotated figure below) and the third element insulating layer (all 29/30 located within the boundaries of the transformer chip, see below) of the transformer chip).
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Regarding Claim 13, Masumura in view of Tanaka teaches the semiconductor device of Claim 12, wherein the insulating layer of the sub-mount chip includes a protective layer formed at a surface layer side of the insulating layer, and wherein in the chip disposition state, the third semiconductor substrate is in contact with the protective layer (Tanaka, fig. 6 teaches sub-mount chip includes a protective layer 29 formed at a surface layer side of the insulating layer (28 of the sub-mount chip, see annotated figure above), and is in contact with the third semiconductor substrate 30 of the transformer chip (see annotated figure above)).
Regarding Claim 20, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, further comprising:
a first die pad that supports the first chip (Masumura, fig. 7 and paragraph 0055, first die pad DPL that supports the first chip CPL);
and a second die pad that supports the second chip (Masumura, second die pad DPH that supports the second chip CPH),
wherein the sub-mount chip and the transformer chip are disposed over the first die pad or the second die pad, between the first chip and the second chip in the first direction (Masumura, fig 7, the transformer chip CPC is disposed over the second die pad DPH and between the first chip CPL and the second chip CPH in the first direction. The combination of Masumura in view of Tanaka teaches a sub-mount into the transformer chip CPC of Masumura).
Claim(s) 6-7 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masumura in view of Tanaka as applied to claim 1-5, 8, 12-13, and 20 above, and further in view of Kurita et al. (US Patent Pub 20220077081 A1).
Regarding Claim 6, Masumura in view of Tanaka teaches the semiconductor device of Claim 1.
Masumura in view of Tanaka fails to teach the semiconductor device wherein a thickness of the sub-mount chip is equal to or greater than a thickness of the transformer chip.
However, Kurita teaches an electronic device having magnetically coupled coils wherein a thickness of the sub-mount chip is equal to or greater than a thickness of the transformer chip (Kurita, Fig. 11, paragraph [0111] teaches that sub-mount chip Ci3 has a thickness equal to or greater than a thickness of transformer chip Ci4).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kurita into the method of Masumura in view of Tanaka by forming the semiconductor device wherein a thickness of the sub-mount chip is equal to or greater than a thickness of the transformer chip. The ordinary artisan would have been motivated to modify Masumura in view of Tanaka in the manner set forth above for at least the purpose of lowering manufacturing cost and increasing manufacturing yield (Kurita, paragraph 0079).
Regarding Claim 7, Masumura in view of Tanaka and in further view of Kurita teaches the semiconductor device of Claim 1, wherein a dimension of the sub-mount chip in the first direction is smaller than a dimension of the transformer chip in the first direction (Kurita, fig. 15 teaches an embodiment of the semiconductor device wherein a dimension of the sub-mount chip Ci2 in the first direction is smaller than a dimension of the transformer chip Ci3 in the first direction).
Regarding Claim 9, Masumura in view of Tanaka and in further view of Kurita teaches the semiconductor device of Claim 1, wherein a dimension of the sub-mount chip in the first direction is larger than a dimension of the transformer chip in the first direction (Kurita, Fig. 13 teaches an embodiment of the semiconductor device wherein a dimension of the sub-mount chip Ci3 in the first direction is larger than a dimension of the transformer chip Ci2 in the first direction).
Regarding Claim 10, Masumura in view of Tanaka and in further view of Kurita teaches the semiconductor device of Claim 1, wherein a thickness of the sub-mount chip is equal to or greater than a thickness of the first chip or a thickness of the second chip (Masumara in view of Tanaka demonstrates a transformer with submount structure adjacent a first and second chip, Kurita, Fig. 14A teaches an embodiment of the semiconductor device wherein a thickness of the sub-mount chip Ci3 is equal to or greater than a thickness an adjacent first or second chip CC).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masumura in view of Tanaka as applied to claim 1-5, 8, 12-13, and 20 above, and further in view of Yoshimura (JP 2009130179 A, see attached machine translation).
Regarding Claim 11, Masumura in view of Tanaka teaches the semiconductor device of Claim 1.
Masumura in view of Tanaka fails to teach the semiconductor device of Claim 1 wherein a thickness of the sub-mount chip is smaller than a thickness of the first chip or a thickness of the second chip.
However, Yoshimura teaches a transformer semiconductor device wherein a thickness of the sub-mount chip is smaller than a thickness of the first chip or a thickness of the second chip (Yoshimura, fig. 14 teaches a sub-mount chip (layers 1/3 of 100, see annotated figure below) that has a smaller thickness than the second chip 300 (See annotated figure below).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Yoshimura into the method of Masumura in view of Tanaka by forming the semiconductor device wherein a thickness of the sub-mount chip is smaller than a thickness of the first chip or a thickness of the second chip. Then ordinary artisan would have been motivated to modify Masumura in view of Tanaka in the manner set forth above for at least the purpose of reducing manufacturing costs (Yoshimura, Abstract and paragraph 0053, see attached machine translation).
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Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masumura in view of Tanaka as applied to claim 1-5, 8, 12-13, and 20 above, and further in view of Kawano (US Patent Pub 20110163824 A1).
Regarding Claim 14, Masumura in view of Tanaka teaches the semiconductor device of Claim 1, wherein the transformer includes an upper coil and lower coil embedded in the third element insulating layer (Tanaka, fig. 6, teaches the transformer includes an upper coil 21 and a lower coil 20 embedded in the third element insulating layer (portion of 27 above the third semiconductor substrate inside the transformer chip, see annotated figure below).
Masumura in view of Tanaka fails to teach the semiconductor device having an outer and inner coil, wherein when viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil.
However, Kawano teaches an inductor device having an outer and inner coil, wherein when viewed from a thickness direction of an insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil (Kawano, fig. 5A and paragraph 0042 teaches an outer coil L1 and inner coil (L2a, L2b, and L2c), wherein when viewed from a thickness direction of an insulating layer, the inner coil (L2a, L2b, and L2c) is disposed inside the outer coil L1 so as not to overlap with the outer coil L1).
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It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kawano into the method of Masumura in view of Tanaka by forming the semiconductor device having an outer and inner coil, wherein when viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil. The ordinary artisan would have been motivated to modify Masumura in view of Tanaka in the manner set forth above for at least the purpose of changing the degree of magnetic coupling between the inductors to meet the desired device performance (Kawano, paragraph 0041).
Regarding Claim 15, Masumura in view of Tanaka and in further view of Kawano teaches the semiconductor device of Claim 14, wherein both the outer coil and the inner coil are disposed on a side farther from the third semiconductor substrate than a center of the third element insulating layer in the thickness direction (Tanaka, fig. 6 teaches an upper coil 21 disposed on a side farther from the third semiconductor substrate (see annotated figure above) than a center of the third element insulating layer (portion of 27 above the third semiconductor substrate inside the transformer chip, see annotated figure above) in the thickness direction. Kawano, fig. 5A and paragraph 0042 teaches an outer coil L1 and inner coil (L2a, L2b, and L2c) disposed in a same layer. Therefore, the combination of Tanaka and Kawano teaches the outer and inner coil disposed in the same layer disposed on a side farther from the third semiconductor substrate than a center of the third element insulating layer in the thickness direction).
Regarding Claim 16, Masumura in view of Tanaka teaches the semiconductor device of Claim 1,
wherein the third element insulating layer includes a structure in which a plurality of insulators, each including a first insulating film containing silicon nitride and a second insulating film containing silicon oxide stacked on the first insulating film, are stacked (Tanaka, Fig. 6 teaches the third element insulating layer (portion of 27 above the third semiconductor substrate inside the transformer chip, see annotated figure above) includes a structure in which a plurality of insulators 28, each including a first insulating film 29 containing silicon nitride (paragraph 0096) and a second insulating film 30 containing silicon oxide (paragraph 0096) stacked on 29, are stacked),
wherein the upper coil is provided so as to penetrate a specific insulator which is a specific one of the insulators (Tanaka, fig. 6, upper coil 21 provided to penetrate a specific one of insulator 28),
wherein the third element insulating layer includes a cover insulating film composed of the first insulating film and in contact with the second insulating film of the specific insulator so as to cover the upper coil (Tanaka, fig. 6, cover insulating film (29 located directly above and covering upper coil 21) which is composed of the first insulating film 29 and in contact with the second insulating film 30 of the specific insulator (portion of 28 surrounding the upper coil 21),
wherein a portion of the first insulating film of the specific insulator between portions of the upper coil includes a plurality of isolation insulating films provided to be spaced apart from each other in a direction orthogonal to the thickness direction of the third element insulating layer (Tanaka, fig. 6, portion of the first insulating film 29 of the specific insulator (portion of 28 covering upper coil 21) includes a plurality of isolation insulating films (portions of 29 disposed between 21) provided to be spaced apart from each other in a direction orthogonal to the thickness direction of the third element insulating layer),
wherein a portion of the cover insulating film between the inner coil and the outer coil includes a plurality of cover side isolation insulating films provided to be spaced apart from each other in the direction orthogonal to the thickness direction (Tanaka, fig. 6, cover side isolation insulating films (portion of 29 located above 37 that are isolated from each other and spaced apart in the direction orthogonal to the thickness direction)),
and wherein each of the plurality of isolation insulating films and the plurality of cover side isolation insulating films includes the second insulating film (Tanaka, fig. 6, each of the plurality of isolation insulating films and the plurality of cover side isolation insulating films (portion of 29 located above 37 that are isolated from each other and spaced apart in the direction orthogonal to the thickness direction) includes the second insulating film 30 (formed above both the plurality of isolation insulating films and the plurality of cover side isolation insulating films).
Masumura in view of Tanaka fail to specifically teach the transformer includes an outer coil and an inner coil, wherein when viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil.
However, Kawano teaches an inductor device having an outer and inner coil, wherein when viewed from a thickness direction of an insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil (Kawano, fig. 5A and paragraph 0042 teaches an outer coil L1 and inner coil (L2a, L2b, and L2c), wherein when viewed from a thickness direction of an insulating layer, the inner coil (L2a, L2b, and L2c) is disposed inside the outer coil L1 so as not to overlap with the outer coil L1).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kawano into the method of Masumura in view of Tanaka by forming the semiconductor device having an outer and inner coil, wherein when viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil. The ordinary artisan would have been motivated to modify Masumura in view of Tanaka in the manner set forth above for at least the purpose of changing the degree of magnetic coupling between the inductors to meet the desired device performance (Kawano, paragraph 0041).
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masumura in view of Tanaka and Kawano as applied to claims 14-16 above, and further in view of Osada et al. (US Patent Pub 20150137314 A1).
Regarding Claim 17, Masumura in view of Tanaka and in further view of Kawano teaches the semiconductor device of Claim 16.
Masumura in view of Tanaka and in further view of Kawano fails to teach the semiconductor device wherein each of the plurality of isolation insulating films and the plurality of cover side isolation insulating films is formed in an annular shape.
However, Osada teaches a semiconductor device with a transformer chip wherein each of the plurality of isolation insulating films and the plurality of cover side isolation insulating films is formed in an annular shape (Osada, Fig. 33 demonstrates a plurality of isolation film portions (portion of 19 spaced apart on the same level as 53) and a plurality of cover side isolation insulating films (portion of 29 spaced apart on the same level as 26, wherein part of one of the segments of 29 is covering coils 21) located in region 48. Fig. 28 demonstrates that region 48 is located on both sides of the coils 21, and are therefore wrapped around and formed annularly about coils 21).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Osada into the method of Masumura in view of Tanaka and Kawano by forming the semiconductor device wherein each of the plurality of isolation insulating films and the plurality of cover side isolation insulating films is formed in an annular shape. The ordinary artisan would have been motivated to modify Masumura in view of Tanaka and Kawano in the manner set forth above for at least the purpose of decreasing leakage current (paragraph 0191).
Regarding Claim 18, Masumura in view of Tanaka teaches the semiconductor device of Claim 1,
wherein the third element insulating layer includes a structure in which a plurality of insulators, each including a first insulating film containing silicon nitride and a second insulating film containing silicon oxide stacked on the first insulating film, are stacked (Tanaka, Fig. 6 teaches the third element insulating layer (portion of 27 above the third semiconductor substrate inside the transformer chip, see annotated figure above) includes a structure in which a plurality of insulators 28, each including a first insulating film 29 containing silicon nitride (paragraph 0096) and a second insulating film 30 containing silicon oxide (paragraph 0096) stacked on 29, are stacked),
wherein the upper coil is provided so as to penetrate a specific insulator which is a specific one of the insulators (Tanaka, fig. 6, upper coil 21 provided to penetrate a specific one of insulator 28),
and wherein the third element insulating layer includes a cover insulating film including the first insulating film and in contact with the second insulating film of the specific insulator so as to cover the upper coil (Tanaka, fig. 6, cover insulating film (29 located directly above and covering upper coil 21) which is composed of the first insulating film 29 and in contact with the second insulating film 30 of the specific insulator (portion of 28 surrounding the upper coil 21).
Masumura in view of Tanaka fails to teach the semiconductor device wherein a portion of the first insulating film of the specific insulator between portions of the upper coil portions includes a plurality of concave portions that are provided to be spaced apart from each other in a direction orthogonal to the thickness direction of the third element insulating layer and open toward the cover insulating film, and wherein a portion of the cover insulating film between portions of the upper coil includes a plurality of cover side concave portions that are provided to be spaced apart from each other in the direction orthogonal to the thickness direction and open toward the first insulating film of the specific insulator, and wherein the second insulating film is embedded in each of the plurality of concave portions and the plurality of cover side concave portions.
However, Osada teaches a semiconductor device with a transformer chip wherein a portion of the first insulating film of the specific insulator between portions of the upper coil portions includes a plurality of concave portions that are provided to be spaced apart from each other in a direction orthogonal to the thickness direction of the third element insulating layer and open toward the cover insulating film (Applicants instant drawing fig. 9 and specification paragraph [0179] demonstrates grooves 72V are concave. Therefore, the grooves of Osada, fig. 33, portion of the first insulating film 29 of the specific insulator (portion of 28 covering upper coil 21) includes a plurality of concave portions 110 that are spaced apart from each other in a direction orthogonal to the thickness direction and open toward the cover insulating film (29 located above and covering upper coils 21),
And wherein a portion of the cover insulating film between portions of the upper coil includes a plurality of cover side concave portions that are provided to be spaced apart from each other in the direction orthogonal to the thickness direction and open toward the first insulating film of the specific insulator, and wherein the second insulating film is embedded in each of the plurality of concave portions and the plurality of cover side concave portions (Osada, fig. 33 teaches a portion of the cover insulating film (portion of 29 directly over and covering upper coil 21) includes a plurality of cover side concave portions (110 between the cover side insulating film) portions that are provided to be spaced apart from each other in the direction orthogonal to the thickness direction and open toward the first insulating film of the specific insulator (the openings open downward toward the first insulating film 29 of the specific insulator (28 including the upper coils 21), and wherein the second insulating film 30 is embedded in each of the plurality of concave portions and the plurality of cover side concave portions).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Osada into the method of Masumura in view of Tanaka by forming the semiconductor device wherein a portion of the first insulating film of the specific insulator between portions of the upper coil portions includes a plurality of concave portions that are provided to be spaced apart from each other in a direction orthogonal to the thickness direction of the third element insulating layer and open toward the cover insulating film, and wherein a portion of the cover insulating film between portions of the upper coil includes a plurality of cover side concave portions that are provided to be spaced apart from each other in the direction orthogonal to the thickness direction and open toward the first insulating film of the specific insulator, and wherein the second insulating film is embedded in each of the plurality of concave portions and the plurality of cover side concave portions (Osada, fig. 33 teaches a portion of the cover insulating film. The ordinary artisan would have been motivated to modify Masumura in view of Tanaka in the manner set forth above for at least the purpose of decreasing leakage current (paragraph 0191).
Masumura in view of Tanaka and in further view of Osada fail to teach the device wherein
the transformer includes an outer coil and an inner coil, wherein when viewed from a thickness direction of an insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil.
However, Kawano teaches an inductor device having an outer and inner coil, wherein when viewed from a thickness direction of an insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil (Kawano, fig. 5A and paragraph 0042 teaches an outer coil L1 and inner coil (L2a, L2b, and L2c), wherein when viewed from a thickness direction of an insulating layer, the inner coil (L2a, L2b, and L2c) is disposed inside the outer coil L1 so as not to overlap with the outer coil L1).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kawano into the method of Masumura in view of Tanaka by forming the semiconductor device having an outer and inner coil, wherein when viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil. The ordinary artisan would have been motivated to modify Masumura in view of Tanaka in the manner set forth above for at least the purpose of changing the degree of magnetic coupling between the inductors to meet the desired device performance (Kawano, paragraph 0041).
Regarding Claim 19, Masumura in view of Tanaka and Kawano and in further view of Osada teaches the semiconductor device of Claim 18, wherein each of the plurality of concave portions and the plurality of cover side concave portions is formed in an annular shape (Osada, Fig. 33 demonstrates a plurality of isolation film portions (portion of 19 spaced apart on the same level as 53) and a plurality of cover side isolation insulating films (portion of 29 spaced apart on the same level as 26, wherein part of one of the segments of 29 is covering coils 21) located in region 48. Fig. 28 demonstrates that region 48 is located on both sides of the coils 21, and are therefore wrapped around and formed annularly about coils 21).
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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