DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites limitations “a collector region”. However, claim 11 also recites “a collector region” (line 3). It is unclear whether the second recited “a collector region” of claim 12 is intended to relate back to “a collector region” recited in claim 11 or to set forth an additional collector region.
Claims 8 and 10 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 8 recites “the metal material is partially over the shallow trench isolation structures”. However, claim 1 (upon which claim 8 depends) recites “the metal material …fully covers shallow trench isolation structures. Thus, claim 8 fails to include all the limitations of the claim upon which it depends.
Claim 10 recites “a dielectric pedestal under the metal material of the extrinsic base region” (as shown in Fig. 11). However, claim 1 (upon which claim 10 depends) recites “the metal material directly contacts and fully covers …a doped region in an underlying semiconductor substrate” as shown in Fig. 7 which does not include “a dielectric pedestal under the metal material of the extrinsic base region”. Thus, claim 10 fails to include all the limitations of the claim upon which it depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,107,124 (hereinafter Patent’124). Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 1 of Patent’124 recites a structure (Col. 7, line 21) comprising:
an intrinsic base region (Col. 7, line 22);
an emitter region (Col. 7, line 24);
a collector region below the emitter region (Col. 7, lines 25-26);
an extrinsic base region comprising metal material adjacent to the intrinsic base region and isolated from the emitter region by sidewall spacers (Col. 7, lines 27-30); and
a first insulator material above a top surface of the emitter region and coplanar with the sidewall spacers and the metal material of the extrinsic base region (Col. 7, lines 31-33), wherein the metal material directly contacts and fully covers shallow trench isolation structures and a doped region in an underlying semiconductor substrate (Col. 7, lines 34-37).
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of Patent’124. Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 10 of Patent’124 recites a structure (Col. 8, line 3) comprising a metal extrinsic base region on sides of an intrinsic base region (Col. 8, lines 13-14) and isolated from an emitter region by sidewall spacers (Col. 8, lines 18-20), a shared contact between a collector region and the metal extrinsic base region (Col. 8, lines 15-17), an insulator material between the sidewall spacers and the emitter region (Col. 8, lines 21-22), and an insulator layer above the emitter region and coplanar with the sidewall spacers and the metal extrinsic base region (Col. 8, lines 24-27).
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of Patent’124. Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 17 of Patent’124 recites a method (Col. 8, line 44) comprising:
forming an intrinsic base region (Col. 8, lines 45-46);
forming an emitter region (Col. 8, line 47);
forming a collector below the emitter region (Col. 8, lines 48-50);
forming an extrinsic base region (Col. 8, line 44) comprising metal material adjacent to the intrinsic base region and isolated from the emitter region by sidewall spacers; and
forming a first insulator material above a top surface of the emitter region and coplanar with the sidewall spacers and the metal material of the extrinsic base region (Col. 8, lines 51-54), wherein the metal material directly contacts and fully covers shallow trench isolation structures and a doped region in an underlying semiconductor substrate (Col. 8, lines 59-62).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,954,457 to Jambotkar in view of Sakai et al. (US Patent No. 5,698,871, hereinafter Sakai) and Isaac et al. (US Patent No. 4,495,512, hereinafter Isaac).
With respect to claims 1 and 2, Jambotkar discloses a structure (e.g., a bipolar transistor) (Jambotkar, Fig. 19, Col. 1, lines 9-11; Col. 2, lines 33-40; Col. 3, lines 49-67; Col. 4, lines 1-3; Col. 6, lines 43-67; Col. 7, lines 1-49) comprising:
an intrinsic base region (e.g., a portion of p-type semiconductor layer 5 under the emitter region 37/38) (Jambotkar, Fig. 19, Col. 3, lines 62-65; Col. 4, lines 52-53);
an emitter region (37/38) (Jambotkar, Fig. 19, Col. 3, lines 62-65; Col. 6, lines 56-65; Col. 7, lines 6-8);
a collector region (3/4) (Jambotkar, Fig. 19, Col. 4, lines 48-51; Col. 6, lines 47-49) below the emitter region (37/38);
an extrinsic base region (e.g., 14/15 and 23/24) (Jambotkar, Fig. 19, Col. 7, lines 11-15; lines 21-24) comprising metal material (23/24) adjacent to the intrinsic base region (e.g., a portion of p-type semiconductor layer 5 under the emitter region 37/38) and isolated from the emitter region (37/38) by sidewall spacers (e.g., portions of the insulating material 26 between sidewalls of the base metal material 23/24 and the emitter region 37/38) (Jambotkar, Fig. 19, Col. 7, lines 27-30); and
wherein the metal material (23/24) (Jambotkar, Fig. 19, Col. 7, lines 27-30) directly contacts and covers shallow trench isolation structures (21) and (fully covers) a doped region (14/15) in an underlying semiconductor substrate (1-5).
Further, Jambotkar does not specifically disclose that (1) a first insulator material above a top surface of the emitter region and coplanar with the sidewall spacers and the metal material of the extrinsic base region (as claimed in claim 1); (2) the metal material fully covers shallow trench isolation structures (as claimed in claim 1); wherein the metal material comprises two metal stacks (as claimed in claim 2).
Regarding (1), Sakai teaches forming a heterojunction bipolar transistor (Sakai, Fig. 2, Col. 1, lines 4-7; Col. 5, lines 44-67; Col. 6, lines 1-37) comprising a first insulator material (11) (Sakai, Fig. 2, Col. 5, lines 47-52) above a top surface of the emitter region (5/6/7) and substantially coplanar with the sidewall spacers (12) and the metal material (8) (Sakai, Fig. 2, Col. 5, lines 7-8; lines 63-67) of the extrinsic base region. In Sasaki, the base metal material (8) is disposed on the extrinsic base layer (16) such that the area of the base layer is reduced, and the base-collector capacitance is reduced to improve high frequency gain of the HBT transistor (Sakai, Fig. 2, Col. 6, lines 19-37).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Jambotkar by forming a first insulator material on the emitter region, and forming the base metal material on the extrinsic base layer as taught by Sakai to have the structure comprising: a first insulator material above a top surface of the emitter region and coplanar with the sidewall spacers and the metal material of the extrinsic base region (as claimed in claim 1), in order to protect the emitter region, and to reduce the base-collector capacitance to improve high frequency gain of the HBT transistor (Sakai, Col. 6, lines 19-37).
Regarding (2), Isaac teaches forming a bipolar transistor structure (Isaac, Fig. 1, Col 1, lines 8-11; Col. 2, lines 2-10; lines 21-28; Col. 3, lines 1-45) comprising an inverted polycide extrinsic base region to reduce the resistivity of the base region, and which is readily etchable down to the silicon oxide, wherein polysilicon layer (7) is formed on top of the metal silicide layer (6) that comprises metal material (e.g., tungsten), wherein the metal material (6) is directly contacting and fully covers shallow trench isolation structures (5) and a doped region (4) in the underlying semiconductor substrate (1), and wherein the metal material (6) (e.g., polycide extrinsic base region 6/7 on both sides of the emitter region 9) (Isaac, Fig. 1, Col 2, lines 52-64) comprises two metal stacks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Jambotkar by forming an inverted polycide extrinsic base region comprising the metal silicide layer directly on the trench isolation region and the doped region as taught by Isaac to have the structure, wherein the metal material fully covers shallow trench isolation structures (as claimed in claim 1); wherein the metal material comprises two metal stacks (as claimed in claim 2), in order to provide improved bipolar transistor with reduced resistance of the base region (Oda, ¶0109; Isaac, Col. 1, lines 8-11; Col. 2, lines 21-28).
Regarding claim 3, Jambotkar in view of Sakai and Isaac discloses the structure of claim 1. Further, Jambotkar discloses the structure, wherein the extrinsic base region (e.g., 14/15) (Jambotkar, Fig. 19, Col. 3, lines 62-65; Col. 4, lines 52-53; Col. 7, lines 11-15; lines 21-24) connects to the intrinsic base region (e.g., a portion of p-type semiconductor layer 5 under the emitter region 37/38) at a sidewall region of the intrinsic base region (5).
Regarding claim 8, Jambotkar in view of Sakai and Isaac discloses the structure of claim 1. Further, Jambotkar discloses the structure, wherein the metal material (e.g., 23/24) (Jambotkar, Fig. 19, Col. 7, lines 11-15; lines 21-24) is partially over the shallow trench isolation structures (21).
With respect to claim 19, Jambotkar discloses a method (e.g., forming a bipolar transistor) (Jambotkar, Figs. 11-19, Col. 1, lines 9-11; Col. 2, lines 33-40; Col. 3, lines 49-67; Col. 4, lines 1-3; Col. 6, lines 43-67; Col. 7, lines 1-49) comprising:
forming an intrinsic base region (e.g., a portion of p-type semiconductor layer 5 under the emitter region 37/38) (Jambotkar, Fig. 19, Col. 3, lines 62-65; Col. 4, lines 52-53);
forming an emitter region (37/38) (Jambotkar, Fig. 19, Col. 3, lines 62-65; Col. 6, lines 56-65; Col. 7, lines 6-8);
forming a collector region (3/4) (Jambotkar, Fig. 19, Col. 4, lines 48-51; Col. 6, lines 47-49) below the emitter region (37/38);
forming an extrinsic base region (e.g., 14/15 and 23/24) (Jambotkar, Fig. 19, Col. 7, lines 11-15; lines 21-24) comprising metal material (23/24) adjacent to the intrinsic base region (e.g., the portion of p-type semiconductor layer 5 under the emitter region 37/38) and isolated from the emitter region (37/38) by sidewall spacers (e.g., portions of the insulating material 26 between sidewalls of the base metal material 23/24 and the emitter region 37/38) (Jambotkar, Fig. 19, Col. 7, lines 27-30); and
wherein the metal material (23/24) (Jambotkar, Fig. 19, Col. 7, lines 27-30) directly contacts and covers shallow trench isolation structures (21) and (fully covers) a doped region (14/15) in an underlying semiconductor substrate (1-5).
Further, Jambotkar does not specifically disclose (1) forming a first insulator material above a top surface of the emitter region and coplanar with the sidewall spacers and the metal material of the extrinsic base region; (2) the metal material fully covers shallow trench isolation structures.
Regarding (1), Sakai teaches forming a heterojunction bipolar transistor (Sakai, Fig. 2, Col. 1, lines 4-7; Col. 5, lines 44-67; Col. 6, lines 1-37) comprising a first insulator material (11) (Sakai, Fig. 2, Col. 5, lines 47-52) above a top surface of the emitter region (5/6/7) and substantially coplanar with the sidewall spacers (12) and the metal material (8) (Sakai, Fig. 2, Col. 5, lines 7-8; lines 63-67) of the extrinsic base region. In Sasaki, the base metal material (8) is disposed on the extrinsic base layer (16) such that the area of the base layer is reduced, and the base-collector capacitance is reduced to improve high frequency gain of the HBT transistor (Sakai, Fig. 2, Col. 6, lines 19-37).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Jambotkar by forming a first insulator material on the emitter region, and forming the base metal material on the extrinsic base layer as taught by Sakai, wherein the metal extrinsic base material and the sidewall spacers have specific thicknesses to have the method comprising: forming a first insulator material above a top surface of the emitter region and coplanar with the sidewall spacers and the metal material of the extrinsic base region, in order to protect the emitter region, and to reduce the base-collector capacitance to improve high frequency gain of the HBT transistor (Sakai, Col. 6, lines 19-37).
Regarding (2), Isaac teaches forming a bipolar transistor structure (Isaac, Fig. 1, Col 1, lines 8-11; Col. 2, lines 2-10; lines 21-28; Col. 3, lines 1-45) comprising an inverted polycide extrinsic base region to reduce the resistivity of the base region, and which is readily etchable down to the silicon oxide, wherein polysilicon layer (7) is formed on top of the metal silicide layer (6) that comprises metal material (e.g., tungsten), wherein the metal material (6) is directly contacting and fully covers shallow trench isolation structures (5) and a doped region (4) in the underlying semiconductor substrate (1), and wherein the metal material (6) (e.g., polycide extrinsic base region 6/7 on both sides of the emitter region 9) (Isaac, Fig. 1, Col 2, lines 52-64) comprises two metal stacks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Jambotkar by forming an inverted polycide extrinsic base region comprising the metal silicide layer directly on the trench isolation region and the doped region as taught by Isaac to have the method, wherein the metal material fully covers shallow trench isolation structures, in order to provide improved bipolar transistor with reduced resistance of the base region (Oda, ¶0109; Isaac, Col. 1, lines 8-11; Col. 2, lines 21-28).
Claims 1-5, 8, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0017399 to Oda et al. (hereinafter Oda) in view of Isaac (US Patent No. 4,495,512).
With respect to claims 1 and 2, Oda discloses a structure (e.g., a bipolar transistor) (Oda, Figs. 1, 5C, 9, 12, ¶0001, ¶0011-¶0014, ¶0048-¶0082, ¶0090-¶0091, ¶0106-¶0109) comprising:
an intrinsic base region (13/14) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091);
an emitter region (20/19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091);
a collector region (12/18) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) below the emitter region (20/19);
an extrinsic base region (e.g., a polysilicon layer 9 and a metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) comprising metal material adjacent to the intrinsic base region (13/14) and isolated from the emitter region (20/19) by sidewall spacers (e.g., 15/16 or 16/17 and a portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0078, ¶0090-¶0091); and
a first insulator material (e.g., a portion of insulating material 21 above a top surface of the emitter region 19) above a top surface of the emitter region (19) and coplanar with the sidewall spacers (e.g., a portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054) and the metal material (e.g., the metal material in the opening of the insulating layer 21) of the extrinsic base region, wherein the metal material contacts and covers shallow trench isolation structures (4) and above a doped region (3) in an underlying semiconductor substrate (1/2).
Further, Oda does not specifically disclose that the metal material directly contacts and fully covers shallow trench isolation structures and a doped region in an underlying semiconductor substrate (as claimed in claim 1); wherein the metal material comprises two metal stacks (as claimed in claim 2).
However, Oda teaches forming an extrinsic base region comprising a titanium silicide film (28) (Oda, Fig. 12, ¶0106-¶0109) on a top surface of the polysilicon layer (9), to reduce the contact resistance of the base electrode.
Further, Isaac teaches forming a bipolar transistor structure (Isaac, Fig. 1, Col 1, lines 8-11; Col. 2, lines 2-10; lines 21-28; Col. 3, lines 1-45) comprising an inverted polycide extrinsic base region to reduce the resistivity of the base region, and which is readily etchable down to the silicon oxide, wherein polysilicon layer (7) is formed on top of the metal silicide layer (6) that comprises metal material (e.g., tungsten), wherein the metal material (6) is directly contacting and fully covers shallow trench isolation structures (5) and a doped region (4) in the underlying semiconductor substrate (1), and wherein the metal material (6) (e.g., polycide extrinsic base region 6/7 on both sides of the emitter region 9) (Isaac, Fig. 1, Col 2, lines 52-64) comprises two metal stacks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Oda by forming an inverted polycide extrinsic base region comprising the metal silicide layer directly on the trench isolation region and the doped region as taught by Isaac, wherein the doped region includes n-type silicon layer of an underlying substrate outside of the intrinsic base region of Oda to have the structure, wherein an extrinsic base region comprises metal material, wherein the metal material directly contacts and fully covers shallow trench isolation structures and a doped region in an underlying semiconductor substrate (as claimed in claim 1); wherein the metal material comprises two metal stacks (as claimed in claim 2), in order to provide improved bipolar transistor with reduced resistance of the base region (Oda, ¶0109; Isaac, Col. 1, lines 8-11; Col. 2, lines 21-28).
Regarding claim 3, Oda in view of Isaac discloses the structure of claim 1. Further, Oda discloses the structure, wherein the extrinsic base region (e.g., the polysilicon layer 9) (Oda, Figs. 1, 9, 12, ¶0054, ¶0091) connects to the intrinsic base region (13/14) at a sidewall region of the intrinsic base region (13/14).
Regarding claim 4, Oda in view of Isaac discloses the structure of claim 1. Further, Oda discloses the structure, wherein the sidewall spacers (e.g., 15/16 and the portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0078, ¶0090-¶0091) separate the extrinsic base region (e.g., the polysilicon layer 9 and the metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) from the intrinsic base region (13/14) and the emitter region (20/19).
Regarding claim 5, Oda in view of Isaac discloses the structure of claim 1. Further, Oda discloses the structure, wherein the sidewall spacers (e.g., 15/16) comprise polysilicon material (15) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0091).
Regarding claim 8, Oda in view of Isaac discloses the structure of claim 1. Further, Oda discloses the structure, wherein the metal material (e.g., the base metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) is partially over the shallow trench isolation structures (4).
Regarding claim 10, Oda in view of Isaac discloses the structure of claim 1. Further, Oda discloses the structure, further comprising a dielectric pedestal (7/8) (Oda, Figs. 1, 5C, 9, ¶0052) under the metal material (e.g., the base metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0054) of the extrinsic base region, and a dedicated collector contact (24) (Oda, Figs. 1, 5C, 9, ¶0051, ¶0054) connecting (e.g., through the extrinsic collector region 5) to the collector region (12/18).
With respect to claim 19, Oda discloses a method (e.g., forming a bipolar transistor) (Oda, Figs. 1, 5C, 9, 12, ¶0001, ¶0011-¶0014, ¶0048-¶0082, ¶0090-¶0091, ¶0106-¶0109) comprising:
forming an intrinsic base region (13/14) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091);
forming an emitter region (20/19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091);
forming a collector region (12/18) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) below the emitter region (20/19);
forming an extrinsic base region (e.g., a polysilicon layer 9 and a metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) comprising metal material adjacent to the intrinsic base region (13/14) and isolated from the emitter region (20/19) by sidewall spacers (e.g., 15/16 or 16/17 and a portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0078, ¶0090-¶0091); and
forming a first insulator material (e.g., a portion of insulating material 21 above a top surface of the emitter region 19) above a top surface of the emitter region (19) and coplanar with the sidewall spacers (e.g., a portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054) and the metal material (e.g., the metal material in the opening of the insulating layer 21) of the extrinsic base region, wherein the metal material contacts and covers shallow trench isolation structures (4) and above a doped region (3) in an underlying semiconductor substrate (1/2).
Further, Oda does not specifically disclose that the metal material directly contacts and fully covers shallow trench isolation structures and a doped region in an underlying semiconductor substrate.
However, Oda teaches forming an extrinsic base region comprising a titanium silicide film (28) (Oda, Fig. 12, ¶0106-¶0109) on a top surface of the polysilicon layer (9), to reduce the contact resistance of the base electrode.
Further, Isaac teaches forming a bipolar transistor structure (Isaac, Fig. 1, Col 1, lines 8-11; Col. 2, lines 2-10; lines 21-28; Col. 3, lines 1-45) comprising an inverted polycide extrinsic base region to reduce the resistivity of the base region, and which is readily etchable down to the silicon oxide, wherein polysilicon layer (7) is formed on top of the metal silicide layer (6) that comprises metal material (e.g., tungsten), wherein the metal material (6) is directly contacting and fully covers shallow trench isolation structures (5) and a doped region (4) in the underlying semiconductor substrate (1), and wherein the metal material (6) (e.g., polycide extrinsic base region 6/7 on both sides of the emitter region 9) (Isaac, Fig. 1, Col 2, lines 52-64) comprises two metal stacks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Oda by forming an inverted polycide extrinsic base region comprising the metal silicide layer directly on the trench isolation region and the doped region as taught by Isaac, wherein the doped region includes n-type silicon layer of an underlying substrate outside of the intrinsic base region of Oda to have the method, wherein the metal material directly contacts and fully covers shallow trench isolation structures and a doped region in an underlying semiconductor substrate, in order to provide improved bipolar transistor with reduced resistance of the base region (Oda, ¶0109; Isaac, Col. 1, lines 8-11; Col. 2, lines 21-28).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,954,457 to Jambotkar in view of Sakai (US Patent No. 5,698,871) and Isaac (US Patent No. 4,495,512) as applied to claim 1, and further in view of Oda (US 2001/0017399).
Regarding claims 4-5, Jambotkar in view of Sakai and Isaac discloses the structure of claim 1. Further, Jambotkar discloses the structure, wherein the sidewall spacers separate the extrinsic base region (23/24) from the emitter region (37/38), but does not specifically disclose that the sidewall spacers separate the extrinsic base region from the intrinsic base region (as claimed in claim 4); wherein the sidewall spacers comprise polysilicon material (as claimed in claim 5).
However, Oda teaches the structure, wherein the sidewall spacers (e.g., 15/16 and the portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0078, ¶0090-¶0091) separate the extrinsic base region (e.g., the polysilicon layer 9 and the metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) from the intrinsic base region (13/14) and the emitter region (20/19), wherein the sidewall spacers (e.g., 15/16) comprise polysilicon material (15) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0091) as link base region to reduce the base resistance of a connection (Oda, Figs. 1, 5C, 9, ¶0040).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Jambotkar/Sakai/Isaac by forming the sidewall spacers including link base region as taught by Oda to have the structure, wherein the sidewall spacers separate the extrinsic base region from the intrinsic base region (as claimed in claim 4); wherein the sidewall spacers comprise polysilicon material (as claimed in claim 5), in order to provide a transistor with reduced base resistance of a connection (Oda, ¶0040).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0017399 to Oda in view of Isaac (US Patent No. 4,495,512) as applied to claim 1, and further in view of Burghartz (US Patent No. 5,059,544).
Regarding claim 6, Oda in view of Isaac discloses the structure of claim 1. Further, Oda discloses the structure, further comprising a contact (22) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0091) to extrinsic base region (9) and the intrinsic base region (13/14) comprises a layer (e.g., p-type semiconductor layer 13/14) of semiconductor material directly of the underlying semiconductor substrate (e.g., 1/2/3), but does not specifically disclose a shared contact to both the extrinsic base region and the collector region.
However, Burghartz discloses forming a bipolar transistor (Burghartz, Fig. 7, Col. 1, lines 8-11; Col. 2, lines 12-21; Col. 3, lines 65-67; Cols. 4-5) comprising a shared contact (e.g., a metallic contact 60, extending through the extrinsic base 34/20 into the collector region 14) (Burghartz, Fig. 7, Col. 5, lines 66-67; Col. 6, lines 1-2) to both the extrinsic base region (34/20) and the collector region (14).
Thus, a person of ordinary skill in the art would recognize that forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz would allow to reduce the size of the transistor. Also, Burghartz teaches that it is desirable to form a transistor with reduced emitter width and base thickness to reduce the base resistance to improve the speed of the transistor (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Oda/Isaac by forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz to have the structure, further comprising a shared contact between the collector region and the extrinsic base region, in order to provide a transistor with reduced size and improved speed (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
Regarding claim 7, Oda in view of Isaac and Burghartz discloses the structure of claim 6. Further, Oda discloses the structure, wherein the contact (22) (Oda, Fig. 12, ¶0054, ¶0106-¶0109) connects to the metal material (e.g., silicide 28) of the extrinsic base region, but does not specifically disclose that the shared contact connects to the metal material of the extrinsic base region.
However, Burghartz discloses forming a bipolar transistor (Burghartz, Fig. 7, Col. 1, lines 8-11; Col. 2, lines 12-21; Col. 3, lines 65-67; Cols. 4-5) comprising a shared contact (e.g., a metallic contact 60, extending through the extrinsic base 34/20 into the collector region 14) (Burghartz, Fig. 7, Col. 5, lines 66-67; Col. 6, lines 1-2) to both the extrinsic base region (34/20) and the collector region (14).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Oda/Isaac/Burghartz by forming the shared contact as taught by Burghartz, wherein the shared contact extending through the metal material of the extrinsic base region to have the structure, wherein the shared contact connects to the metal material of the extrinsic base region, in order to provide improved transistor with reduced resistance of the base region, and with reduced size and improved speed (Oda, ¶0109; Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,954,457 to Jambotkar in view of Sakai (US Patent No. 5,698,871) and Isaac (US Patent No. 4,495,512) as applied to claim 1, and further in view of Burghartz (US Patent No. 5,059,544).
Regarding claim 6, Jambotkar in view of Sakai and Isaac discloses the structure of claim 1. Further, Jambotkar does not specifically disclose a shared contact to both the extrinsic base region and the collector region.
However, Burghartz discloses forming a bipolar transistor (Burghartz, Fig. 7, Col. 1, lines 8-11; Col. 2, lines 12-21; Col. 3, lines 65-67; Cols. 4-5) comprising a shared contact (e.g., a metallic contact 60, extending through the extrinsic base 34/20 into the collector region 14) (Burghartz, Fig. 7, Col. 5, lines 66-67; Col. 6, lines 1-2) to both the extrinsic base region (34/20) and the collector region (14).
Thus, a person of ordinary skill in the art would recognize that forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz would allow to reduce the size of the transistor. Also, Burghartz teaches that it is desirable to form a transistor with reduced emitter width and base thickness to reduce the base resistance to improve the speed of the transistor (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Jambotkar/Sakai/Isaac by forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz to have the structure, further comprising a shared contact between the collector region and the extrinsic base region, in order to provide a transistor with reduced size and improved speed (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
Regarding claim 7, Jambotkar in view of Sakai, Isaac, and Burghartz discloses the structure of claim 6. Further, Jambotkar discloses the structure, wherein the contact (22) (Oda, Fig. 12, ¶0054, ¶0106-¶0109) connects to the metal material (e.g., silicide 28) of the extrinsic base region, but does not specifically disclose that the shared contact connects to the metal material of the extrinsic base region.
However, Burghartz discloses forming a bipolar transistor (Burghartz, Fig. 7, Col. 1, lines 8-11; Col. 2, lines 12-21; Col. 3, lines 65-67; Cols. 4-5) comprising a shared contact (e.g., a metallic contact 60, extending through the extrinsic base 34/20 into the collector region 14) (Burghartz, Fig. 7, Col. 5, lines 66-67; Col. 6, lines 1-2) to both the extrinsic base region (34/20) and the collector region (14).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Jambotkar/Sakai/Isaac/Burghartz by forming the shared contact as taught by Burghartz, wherein the shared contact extending through the metal material of the extrinsic base region to have the structure, wherein the shared contact connects to the metal material of the extrinsic base region, in order to provide improved transistor with reduced resistance of the base region, and with reduced size and improved speed (Oda, ¶0109; Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0017399 to Oda in view of Isaac (US Patent No. 4,495,512) as applied to claim 1, and further in view of Naem (US Patent No. 6,529,861).
Regarding claim 9, Oda in view of Isaac discloses the structure of claim 1. Further, Oda does not specifically disclose that the collector region is devoid of a dedicated collector contact region.
However, Naem teaches forming a bipolar transistor (Naem, Fig. 3I, Col. 1, lines 14-18; Col. 2, lines 29-48; Col. 4, lines 31-67; Col. 5, lines 1-8) having an ultra-small emitter to reduce maximum current that flows through the transistor, and with reduced power consumption and base-to emitter capacitance by limiting the base-to-emitter contact area. The bipolar transistor of Naem comprises a collector region (304) (Naem, Fig. 3I, Col. 4, lines 31-33; Col. 5, lines 5-8) under the extrinsic base (322), and the silicide contact (324) on the extrinsic base region (322).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Oda/Isaac by forming a contact to the extrinsic base and the collector formed under the extrinsic base as taught by Naem to have the structure, wherein the collector region is devoid of a dedicated collector contact region, in order to provide improved bipolar transistor having an ultra-small emitter to reduce maximum current that flows through the transistor, and with reduced power consumption and base-to emitter capacitance by limiting the base-to-emitter contact area (Naem, Col. 1, lines 14-18; Col. 2, lines 29-48; Col. 5, lines 1-8).
Claims 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0017399 to Oda in view of Isaac (US Patent No. 4,495,512) and Burghartz (US Patent No. 5,059,544).
With respect to claim 11, Oda discloses a structure (e.g., a bipolar transistor) (Oda, Figs. 1, 5C, 9, 12, ¶0001, ¶0011-¶0014, ¶0048-¶0082, ¶0090-¶0091, ¶0106-¶0109) comprising a metal extrinsic base region (e.g., a metal material in the opening of the insulating layer 21 and connected to the extrinsic base polysilicon layer 9) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0091) on a side of an intrinsic base region (e.g., 13/14) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091) and isolated from an emitter region (20/19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091) by sidewall spacers (e.g., 15/16/10 and a portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091), an insulator material (17) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0078, ¶0090) between the sidewall spacers (15/16/10) and the emitter region (19), and an insulator layer (e.g., a portion of insulating material 21 above the emitter region 19) above the emitter region (19) and coplanar with the sidewall spacers (e.g., a portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054) and the metal extrinsic base region (e.g., the metal material in the opening of the insulating layer 21 and connected to the extrinsic base polysilicon layer 9) (Oda, Figs. 1, 5C, 9, ¶0054).
Further, Oda does not specifically disclose (1) a metal extrinsic base region on sides of an intrinsic base region; (2) a shared contact between a collector region and the metal extrinsic base region.
Regarding (1), Oda teaches forming an extrinsic base region comprising a titanium silicide film (28) (Oda, Fig. 12, ¶0106-¶0109) on a top surface of the polysilicon layer (9), to reduce the contact resistance of the base electrode.
Further, Isaac teaches forming a bipolar transistor structure (Isaac, Fig. 1, Col 1, lines 8-11; Col. 2, lines 2-10; lines 21-28; Col. 3, lines 1-45) comprising an inverted polycide extrinsic base region to reduce the resistivity of the base region, and which is readily etchable down to the silicon oxide, wherein polysilicon layer (7) is formed on top of the metal silicide layer (6) that comprises metal material (e.g., tungsten), and an insulator layer (8) is formed on the polysilicon layer (7), wherein the metal material (6) is directly contacting and fully covers shallow trench isolation structures (5) formed in the underlying semiconductor substrate (1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Oda by forming an inverted polycide extrinsic base region comprising the metal silicide layer on the trench isolation structures, polysilicon layer on the metal silicide layer as taught by Isaac, wherein the metal silicide layer is formed on sides of an intrinsic base region of Oda to have the structure comprising a metal extrinsic base region on sides of an intrinsic base region, in order to provide improved bipolar transistor with reduced resistance of the base region (Oda, ¶0109; Isaac, Col. 1, lines 8-11; Col. 2, lines 21-28).
Regarding (2), Burghartz teaches forming a bipolar transistor (Burghartz, Fig. 7, Col. 1, lines 8-11; Col. 2, lines 12-21; Col. 3, lines 65-67; Cols. 4-5) comprising a shared contact (e.g., a metallic contact 60, extending through the extrinsic base 34/20 to the collector region 14) between the collector region (14) (Burghartz, Fig. 7, Col. 5, lines 66-67; Col. 6, lines 1-2) and the extrinsic base region (34/20).
Thus, a person of ordinary skill in the art would recognize that forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz would allow to reduce the size of the transistor. Also, Burghartz teaches that it is desirable to form a transistor with reduced emitter width and base thickness to reduce the base resistance to improve the speed of the transistor (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Oda/Isaac by forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz to have a shared contact between a collector region and the metal extrinsic base region, in order to provide a transistor with reduced size and improved speed (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
Regarding claim 12, Oda in view of Isaac and Burghartz discloses the structure of claim 11. Further, Oda discloses the structure, further comprising a collector region (18/12) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) and trench isolation structures (4) isolating the collector region, wherein the intrinsic base region (13/14) is over the collector region (18/12) and between the trench isolation structures (4).
Regarding claim 13, Oda in view of Isaac and Burghartz discloses the structure of claim 12. Further, Oda discloses the structure, wherein the metal extrinsic base region (e.g., the base metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) partially overlaps the shallow trench isolation structures (4).
Regarding claim 14, Oda in view of Isaac and Burghartz discloses the structure of claim 12. Further, Oda does not specifically disclose that the metal extrinsic base region fully overlaps the trench isolation structures. However, Isaac teaches forming a bipolar transistor structure (Isaac, Fig. 1, Col. 1, lines 8-11; Col. 2, lines 2-10; lines 21-28; Col. 3, lines 1-45) comprising an inverted polycide extrinsic base region to reduce the resistivity of the base region, wherein the metal material (e.g., metal silicide layer 6) is directly contacting and fully covers shallow trench isolation structures (5) formed in the underlying semiconductor substrate (1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Oda/Isaac/Burghartz by forming an inverted polycide extrinsic base region comprising the metal silicide layer on the trench isolation structures, polysilicon layer on the metal silicide layer as taught by Isaac to have the structure, wherein the metal extrinsic base region fully overlaps the trench isolation structures, in order to provide improved bipolar transistor with reduced resistance of the base region (Oda, ¶0109; Isaac, Col. 1, lines 8-11; Col. 2, lines 21-28).
Regarding claim 15, Oda in view of Isaac and Burghartz discloses the structure of claim 11. Further, Oda discloses the structure, wherein the sidewall spacers (e.g., 15/16/10 and a portion of the insulating material 21 between sidewalls of the base metal material and the emitter region 19) (Oda, Figs. 1, 5C, 9, ¶0054, ¶0090-¶0091) separate the intrinsic base region (13/14) and the emitter region (20/19) from the metal extrinsic base region (e.g., the metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091).
Regarding claim 16, Oda in view of Isaac and Burghartz discloses the structure of claim 11. Further, Oda does not specifically disclose that the metal extrinsic base region comprises gate metal material.
However, Isaac teaches forming a bipolar transistor structure (Isaac, Fig. 1, Col. 1, lines 8-11; Col. 2, lines 2-10; lines 21-28; Col. 3, lines 1-45) comprising an inverted polycide extrinsic base region to reduce the resistivity of the base region, wherein the metal material (e.g., metal silicide layer 6) is directly contacting and fully covers shallow trench isolation structures (5) formed in the underlying semiconductor substrate (1) and separated from the emitter (9) with a portion of the insulator material (8), wherein the metal extrinsic base region (e.g., metal silicide 6 comprised of tungsten silicide) comprises gate metal material (e.g., a tungsten (W) material is interpreted as gate metal material).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Oda/Isaac/Burghartz by forming an inverted polycide extrinsic base region comprising the metal silicide layer on the trench isolation structures, polysilicon layer on the metal silicide layer as taught by Isaac to have the structure, wherein the metal extrinsic base region comprises gate metal material, in order to provide improved bipolar transistor with reduced resistance of the base region (Oda, ¶0109; Isaac, Col. 1, lines 8-11; Col. 2, lines 21-28).
Regarding claim 17, Oda in view of Isaac and Burghartz discloses the structure of claim 11. Further, Oda discloses the structure, wherein the intrinsic base region (13/14) (Oda, 1, 5C, 9, 12, ¶0054) comprises SiGe.
Regarding claim 18, Oda in view of Isaac and Burghartz discloses the structure of claim 11. Further, Oda discloses the structure, wherein the metal extrinsic base region (e.g., the base metal material in the opening of the insulating layer 21) (Oda, Figs. 1, 5C, 9, ¶0053-¶0054, ¶0090-¶0091) connects (e.g., through the polysilicon layer 9 and the link spacers 15) to the intrinsic base region (13/14) at a sidewall region.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 5,698,871 to Sakai in view of Burghartz (US Patent No. 5,059,544).
With respect to claim 11, Sakai discloses a structure (e.g., a bipolar transistor) (Sakai, Fig. 2, Col. 1, lines 4-7; Col. 5, lines 44-67; Col. 6, lines 1-37) comprising a metal extrinsic base region (e.g., metal extrinsic base regions 8) (Sakai, Fig. 2, Col. 5, lines 7-8; lines 63-67) on sides of an intrinsic base region (e.g., 4, under the emitter region 5/6/7) and isolated from an emitter region (5/6/7) (Sakai, Fig. 2, Col. 5, lines 48-50) by sidewall spacers (e.g., portions of semiconductor material 16 between sidewalls of the base metal material 8 and the emitter region 5/6/7), an insulator material (12) between the sidewall spacers (e.g., portions of semiconductor material 16) and the emitter region (5/6/7), and an insulator layer (e.g., 11) (Sakai, Fig. 2, Col. 5, lines 47-48) above the emitter region (5/6/7).
Further, Sakai does not specifically disclose (1) a shared contact between a collector region and the metal extrinsic base region; (2) an insulator layer coplanar with the sidewall spacers and the metal extrinsic base region.
Regarding (1), Burghartz teaches forming a bipolar transistor (Burghartz, Fig. 7, Col. 1, lines 8-11; Col. 2, lines 12-21; Col. 3, lines 65-67; Cols. 4-5) comprising a shared contact (e.g., a metallic contact 60, extending through the extrinsic base 34/20 to the collector region 14) between the collector region (14) (Burghartz, Fig. 7, Col. 5, lines 66-67; Col. 6, lines 1-2) and the extrinsic base region (34/20).
Thus, a person of ordinary skill in the art would recognize that forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz would allow to reduce the size of the transistor. Also, Burghartz teaches that it is desirable to form a transistor with reduced emitter width and base thickness to reduce the base resistance to improve the speed of the transistor (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Sakai by forming a shared contact extending through the extrinsic base to the collector region as taught by Burghartz to have a shared contact between a collector region and the metal extrinsic base region, in order to provide a transistor with reduced size and improved speed (Burghartz, Fig. 7, Col. 1, lines 21-25; Col. 2, lines 66-67).
Regarding (2), Sakai teaches forming a heterojunction bipolar transistor (Sakai, Fig. 2, Col. 1, lines 4-7; Col. 5, lines 44-67; Col. 6, lines 1-37) comprising a first insulator material (11) (Sakai, Fig. 2, Col. 5, lines 47-52) above a top surface of the emitter region (5/6/7) and substantially coplanar with the metal extrinsic base region (8) (Sakai, Fig. 2, Col. 5, lines 7-8; lines 63-67). In Sasaki, the metal extrinsic base region (8) is disposed on the extrinsic base layer (16) such that the area of the base layer is reduced, and the base-collector capacitance is reduced to improve high frequency gain of the HBT transistor (Sakai, Fig. 2, Col. 6, lines 19-37).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Sakai by forming the metal extrinsic base material on the extrinsic base layer as taught by Sakai, wherein the metal extrinsic base material and the sidewall spacers have specific thicknesses to have the structure comprising an insulator layer coplanar with the sidewall spacers and the metal extrinsic base region, in order to protect the emitter region, and to reduce the base-collector capacitance to improve high frequency gain of the HBT transistor (Sakai, Col. 6, lines 19-37).
Regarding claim 12, Sakai in view of Burghartz discloses the structure of claim 11. Further, Sakai discloses the structure, further comprising a collector region (2/3) (Sakai, Fig. 2, Col. 4, lines 49-55; Col. 5, lines 52-54) and trench isolation structures (e.g., openings in the collector layer 3) isolating the collector region (e.g., a portion of the collector layer 3), wherein the intrinsic base region (4) is over the collector region (3) and between the trench isolation structures (e.g., openings in the collector layer 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
Prosecution Insights