CTNF 18/790,090 CTNF 87109 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 – 13, and 17 - 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Shin et al. (U.S. Patent Publication No. 2011/0164391) . Regarding claim 1, in Figure 15, Shin discloses a printed circuit board (200) comprising: a substrate (110; comprising lower and upper substrates 110) having a cavity (130); a semiconductor device (140, top electronic component 140) at least partially disposed in the cavity, with a first metal pad (145, lower terminal 145) being disposed on a lower side of the semiconductor device and a second metal pad (145, upper terminal 145) being disposed on an upper side of the semiconductor device; a metal block (165) at least partially disposed in the cavity, the metal block being connected to the second metal pad; and a first insulating layer (150) covering at least a portion of each of the substrate, the semiconductor device, and the metal block (insulating layer 150 covers the side surfaces of via 165), and filling at least a portion of the cavity. Regarding claim 2, Shin discloses wherein the semiconductor device includes a power MOSFET, the first metal pad includes a source pad, the second metal pad includes a drain pad, and a gate is further disposed on the lower side of the semiconductor device (Figure 15). Regarding claim 3, Shin discloses wherein the metal block is directly connected to the second metal pad (Figure 15). Regarding claim 4, Shin discloses wherein each of the second metal pad and the metal block includes copper, and the copper of the second metal pad and the copper of the metal block are joined to each other and directly connected to each other (Figure 15). Regarding claim 5, Shin discloses wherein the cavity penetrates between upper and lower surfaces of the substrate in a thickness direction, and the metal block is attached to the upper side of the semiconductor device, and at least a portion of the metal block is disposed in the cavity together with the semiconductor device (Figure 15). Regarding claim 6, Shin discloses wherein the cavity includes a first cavity penetrating at least a portion of the substrate from a lower surface of the substrate in a thickness direction, and a second cavity penetrating at least another portion of the substrate from an upper surface of the substrate in the thickness direction, at least a portion of the semiconductor device is disposed in the first cavity, and at least a portion of the metal block is disposed in the second cavity (Figure 15). Regarding claim 7, Shin discloses wherein the first and second cavities have different widths in a cross-sectional view, and the semiconductor device and the metal block have different widths in a cross-sectional view (Figure 15). Regarding claim 8, Shin discloses wherein the first and second cavities are connected to each other in the thickness direction (Figure 15). Regarding claim 9, Shin discloses wherein the substrate is disposed between the first and second cavities to separate the first and second cavities from each other (Figure 15). Regarding claim 10, Shin discloses wherein the metal block includes a first metal block at least partially disposed in the first cavity, the first metal block being connected to the second metal pad, a second metal block of at least partially disposed in the second cavity, the second metal block being attached onto the substrate disposed between the first and second cavities through an adhesive, and a metal via penetrating the substrate disposed between the first and second cavities and the adhesive and connecting the first and second metal blocks to each other v. Regarding claim 11, Shin discloses a first wiring layer disposed on a lower surface of the substrate; a second wiring layer disposed on an upper surface of the substrate; and a first via layer penetrating the substrate, and connecting the first and second wiring layers to each other (Figure 15). Regarding claim 12, Shin discloses a third wiring layer disposed on a lower surface of the first insulating layer; a second via layer penetrating at least a portion of the first insulating layer on a lower side thereof, and connecting the third wiring layer to each of the first wiring layer and the first metal pad; a fourth wiring layer disposed on an upper surface of the first insulating layer; and a third via layer penetrating at least a portion of the first insulating layer on an upper side thereof, and connecting the fourth wiring layer to each of the second wiring layer and the second metal pad (Figure 15). Regarding claim 13, Shin discloses wherein the substrate includes an organic core layer, a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer (Figure 15). Regarding claim 17, in Figure 15, Shin discloses a printed circuit board, comprising: a substrate (110; comprising lower and upper substrates 110) having a first cavity (130) disposed in a first surface (bottom surface of lower substrate 110) thereof and a second cavity (130) disposed in a second surface (top surface of upper substrate 110) thereof, the first and second cavities at least partially overlapping in a plan view; a semiconductor device (140, upper component 140) disposed at least partially in the first cavity and having a first metal pad (145, lower terminal 145) disposed on a first side (bottom side of lower component 140) thereof and a second metal pad (145, upper terminal 145) disposed on a second side (top side of upper component 140) thereof; a metal block (165) at least partially disposed in the second cavity and directly contacting the second metal pad of the semiconductor device; and a first insulating layer (150) disposed on the first and second surfaces of the substrate, at least partially covering the substrate, the semiconductor device and the metal block at least partially filling the first and second cavities (Figure 15). Regarding claim 18, Shin discloses wherein at least a portion of the first and second cavities are connected in a cross-sectional view to form at least one through-hole penetrating through the substrate (Figure 15). Regarding claim 19, Shin discloses wherein the first and second cavities have different widths in a cross-sectional view, and the semiconductor device and the metal block have different widths in the cross-sectional view (Figure 15). Regarding claim 20, Shin discloses a first wiring layer disposed on the first surface of the substrate; a second wiring layer disposed on the second surface of the substrate; and a first via layer penetrating the substrate, and connecting the first and second wiring layers to each other (Figure 15) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 14 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Shin . Regarding claim 14, in Figure 15, Shin discloses a printed circuit board (200) comprising: a substrate (110; comprising lower and upper substrates 110) having a through-cavity (130); a laminate (comprising 140, 145, 165, 120) at least partially disposed in the through-cavity, the laminate including a power device (140, top electronic component 140) with a first metal pad (145, lower terminal 145) and a gate being disposed on a first side (bottom side) of the power device and a second metal pad (145, upper terminal 145) being disposed on a second side (top side) of the power device, and a metal block (165) disposed on the power device and contacting the second metal pad; and an insulating layer (150) covering at least a portion of each of the substrate and the laminate, and filling at least a portion of the through-cavity (Figure 15). Shin does not specifically disclose electronic component 140 being a power device having a gate disposed on the bottom side. However, providing a printed circuit board with various electronic components, such as a power device having a gate, is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill. Regarding claim 15, Shin discloses first and second metal pattern layers disposed on the first side and the second side of the insulating layer, respectively; a first metal via penetrating at least a portion of the insulating layer, and connecting at least a portion of the first metal pattern layer to the first metal pad; a second metal via penetrating at least another portion of the insulating layer, and connecting at least another portion of the first metal pattern layer to the gate; and a third metal via penetrating at least another portion of the insulating layer, and connecting at least a portion of the second metal pattern layer to the metal block (Figure 15). Regarding claim 16, Shin discloses wherein the metal block is thicker than the power device (Figure 15). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847 Application/Control Number: 18/790,090 Page 2 Art Unit: 2847 Application/Control Number: 18/790,090 Page 3 Art Unit: 2847 Application/Control Number: 18/790,090 Page 4 Art Unit: 2847 Application/Control Number: 18/790,090 Page 5 Art Unit: 2847 Application/Control Number: 18/790,090 Page 6 Art Unit: 2847 Application/Control Number: 18/790,090 Page 7 Art Unit: 2847 Application/Control Number: 18/790,090 Page 8 Art Unit: 2847 Application/Control Number: 18/790,090 Page 9 Art Unit: 2847
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