DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 16, 2026 have been fully considered but are moot because new grounds of rejection have been made.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2)
Regarding Claim 1 – Kubo teaches a circuit board (Figs 1-3; MB1) comprising: a first surface having a first mounting region configured so that a first electronic part is mounted or mountable to the first mounting region (Figs 1, 3; SP1 mounted over MB1 upper surface Ma); and a second surface having a second mounting region configured so that a second electronic part is mounted or mountable to the second mounting region, the second surface being different from the first surface (Figs 2-3; capacitor CP1 mounted over MB1 lower surface Mb); wherein the circuit board includes an overlapping region in which the first mounting region and the second mounting region overlap each other as viewed from a direction perpendicular to the first surface (Figs 2-3; SP1 above CP1; Kubo [0060, 0086]), and wherein the first through via penetrating through the circuit board is arranged in the overlapping region (Figs 3, 9-10; TH1d/TH1s).
Kubo does not explicitly disclose a plurality of through vias penetrating through the circuit board, including at least a first through via and a second through via, and the second through via penetrating through the circuit board has an opening area different from an opening area of the first through via penetrating through the circuit board.
Len teaches a plurality of through vias penetrating through the circuit board, including at least a first through via and a second through via (Figs 1A, 2A; 104, 106A-G, 202, 210), and the second through via penetrating through the circuit board has an opening area different from an opening area of the first through via penetrating through the circuit board (Fig 8; 802/804, 806).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo with a plurality of through vias penetrating through the circuit board, including at least a first through via and a second through via, and the second through via penetrating through the circuit board has an opening area different from an opening area of the first through via penetrating through the circuit board as taught by Len because Len teaches that “each drill iteration can have a different drill diameter, which can be larger or smaller than the previous drill” and that “By overlapping the via patterns from different iterations, the via density may be increased”.
Regarding Claim 16 – Kubo in view of Len teaches the circuit board according to claim 1, wherein the second through via penetrating through the circuit board is arranged outside the overlapping region in which the first through via penetrating through the circuit board is arranged (Kubo Fig 3; through hole TH3, semiconductor device SP1; Kubo [0066]), and wherein the opening area of the second through via is larger than the opening area of the first through via (Len Fig 8; 802/804, 806).
Claims 2, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), and in further view of Sugimura (US 7606038 B2) and Min et al. (US 10015877 B2)
Regarding Claim 2 – Kubo in view of Len teaches the circuit board according to claim 1, but does not explicitly disclose further comprising: a first heat transfer pattern to which the first electronic part is adherable; and a second heat transfer pattern to which the second electronic part is adherable, wherein the first through via connects the first heat transfer pattern and the second heat transfer pattern to each other.
Sugimura teaches a first heat transfer pattern to which the first electronic part is adherable (Sugimura Fig 2(B) teaches soldering land 22 for heat radiation on first surface 12a, land 22 “serves as a mounting surface for an electronic part”; also, solder layer 27 is provided “between the soldering land 22 for heat radiation and the heat sink 21 on the side where the electronic part 20 is to be mounted”); and, wherein the first through via connects the first heat transfer pattern and the second heat transfer pattern to each other (Sugimura Figs 1(A)-2(B) teaches viaholes 24 formed through the substrate 12 between soldering land 22 and land 25).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len with a first heat transfer pattern to which the first electronic part is adherable and, wherein the first through via connects the first heat transfer pattern and the second heat transfer pattern to each other as taught by Sugimura because Sugimura teaches that its heat radiating structure is “particularly designed to improve the heat radiating capability of a heat generating electronic part” wherein heat is transferred through the heat transfer pattern and viaholes and radiated from the opposite side.
Min teaches a second heat transfer pattern to which the second electronic part is adherable (Fig 1; circuit board 100 having a first heat transfer structure 110, first via V1 and second via V2 in contact with 110, first metal pattern 131, second metal pattern 141, electronic components 500 and 200; Min teaches heat transfer through “the first metal pattern 131-the first via V1-the first heat transfer structure 110-the second via V2-the second metal pattern 141”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len with a second heat transfer pattern to which the second electronic part is adherable as taught by Min to get the benefit of improved heat transfer through connected opposite-side thermal structures.
Regarding Claim 4 – Kubo in view of Len, Sugimura, and Min teaches the circuit board according to claim 2, wherein the first through via is formed in a region in which the first heat transfer pattern and the second heat transfer pattern overlap each other as viewed from the direction (Sugimura Fig 2(B); viaholes 24 between soldering land 22 for heat radiation and land 25 for solder absorption).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), Sugimura (US 7606038 B2), and Min et al. (US 10015877 B2), and in further view of Nakazawa et al. (US 20140174795 A1)
Regarding Claim 3 – Kubo in view of Len, Sugimura, and Min teaches the circuit board according to claim 2, but does not explicitly disclose wherein the first heat transfer pattern has a size larger than a size of the second heat transfer pattern.
Nakazawa teaches the first heat transfer pattern has a size larger than a size of the second heat transfer pattern (Figs 1A-1B; heat transfer pattern 111, conductive patterns 133, 134; Nakazawa [0035] states “The conductive pattern 133 arranged on the surface layer 102 and the conductive pattern 134 arranged on the inner layer 103 are planate conductive patterns, have larger areas than that of the heat transfer pattern 111, and have larger heat capacities than that of the heat transfer pattern 111”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len, Sugimura, and Min with the first heat transfer pattern has a size larger than a size of the second heat transfer pattern as taught by Nakazawa because Nakazawa teaches that by using the larger area conductive patterns 133 and 134 “the heat transfer pattern 111 can effectively radiate the heat… to the conductive patterns 133 and 134”.
Claims 5, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), Sugimura (US 7606038 B2), and Min et al. (US 10015877 B2), and in further view of Suzuki et al. (US 20160366757 A1)
Regarding Claim 5 – Kubo in view of Len, Sugimura and Min teaches the circuit board according to claim 2, but does not explicitly disclose wherein the second through via is formed in a region in which the first mounting region and the second mounting region do not overlap each other as viewed from the direction.
Suzuki teaches the second through via is formed in a region in which the first mounting region and the second mounting region do not overlap each other as viewed from the direction (Fig 2; penetration hole 7, non-overlapping region P, mounting regions Ra to Rj; Suzuki [0076-0077, 0103]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len, Sugimura and Min with the second through via is formed in a region in which the first mounting region and the second mounting region do not overlap each other as viewed from the direction as taught by Suzuki because Suzuki teaches placing the penetration hole in “P not overlapping the mounting regions Ra to Rj and the wiring patterns 5a to 5w” so the board can be fixed in a region outside the component mounting regions and wiring patterns (Suzuki [0076]).
Regarding Claim 7 – Kubo in view of Len, Sugimura, Min, and Suzuki teaches the circuit board according to claim 5, wherein the number of the first through vias is larger than the number of the second through vias (Len Figs 3A-5B; first drilling pattern 300A, second drilling pattern 400A; Len teaches a “first plurality of through-holes or vias” and a “second plurality of through-holes or vias” and further teaches that “a first drilling pattern 300A includes twenty-seven PTHs or filled vias” while “the second drilling pattern 400 includes twenty-two PTHs or filled vias”).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), Sugimura (US 7606038 B2), and Min et al. (US 10015877 B2), and in further view of Yuhara et al. (JP 4489112 B2)
Regarding Claim 6 – Kubo in view of Len, Sugimura and Min teaches the circuit board according to claim 2, but does not explicitly disclose further comprising a heat dissipation path connecting the second through via and the second heat transfer pattern to each other, the heat dissipation path being covered with a solder resist.
Yuhara teaches a heat dissipation path connecting the second through via and the second heat transfer pattern to each other, the heat dissipation path being covered with a solder resist (Figs 5, 7a, 7b; heat transfer patterns 13 and 14, heat transfer through hole 15, solder resist film 18; Yuhara [0018-0020]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len, Sugimura and Min with a heat dissipation path connecting the second through via and the second heat transfer pattern to each other, the heat dissipation path being covered with a solder resist as taught by Yuhara because Yuhara [0026-0027] states “the spacing between the second heat transfer pattern and the heat transfer pedestal can be secured to a stable size… so that excellent heat transfer and heat dissipation characteristics can be achieved” and “the heat transfer connection between the first and second heat transfer patterns can be made by simple means”.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), and in further view of Tsuchiya et al. (JP 7390835 B2)
Regarding Claim 11 – Kubo in view of Len teaches the circuit board according to claim 1, wherein the circuit board has a multilayer structure, wherein the first through via and the second through via are configured to dissipate heat of the first electronic part to another layer, and wherein the first through via is configured to dissipate heat of the second electronic part to another layer.
Tsuchiya teaches the circuit board has a multilayer structure (Figs 1-6(b); Tsuchiya [0019]), wherein the first through via and the second through via are configured to dissipate heat of the first electronic part to another layer (Figs 3-6(b); through vias 81, 82, heat transfer patterns 71, 72, heat radiation pattern 6; Tsuchiya [0023-0024, 0026]), and wherein the first through via is configured to dissipate heat of the second electronic part to another layer (Figs 3-6(b); through vias 81, 82, heat transfer patterns 71, 72, heat radiation pattern 6; Tsuchiya [0023-0024]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len with the circuit board has a multilayer structure, wherein the first through via and the second through via are configured to dissipate heat of the first electronic part to another layer, and wherein the first through via is configured to dissipate heat of the second electronic part to another layer as taught by Tsuchiya because Tsuchiya [0026] states “the efficiency of discharging the heat generated in the heat generating component 3 can be increased” by using heat transfer patterns and through vias to conduct heat to another layer and the backside heat radiation pattern.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), Sugimura (US 7606038 B2), and Min et al. (US 10015877 B2), and in further view of Nakazawa et al. (US 20140174795 A1)
Regarding Claim 12 – Kubo in view of Len, Sugimura and Min teaches the circuit board according to claim 2, wherein the first electronic part… include a heat dissipation plate, wherein the heat dissipation plate of the first electronic part is adherable to the first heat transfer pattern (Sugimura Figs 5-6 teaches electronic part 20, heat sink 21, soldering land 22 for heat radiation, and cream solder on 22 melts to adhere to heat sink 21 to soldering land 22 and become soldering layers 27).
Kubo in view of Len, Sugimura and Min does not explicitly disclose the second electronic part include a heat dissipation plate, and wherein the heat dissipation plate of the second electronic part is adherable to the second heat transfer pattern.
Nakazawa teaches the second electronic part include a heat dissipation plate, and wherein the heat dissipation plate of the second electronic part is adherable to the second heat transfer pattern (Figs 1A-1B; 200, 202, 111, 150; Nakazawa [0028, 0031, 0033]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len, Sugimura and Min with the second electronic part include a heat dissipation plate, and wherein the heat dissipation plate of the second electronic part is adherable to the second heat transfer pattern as taught by Nakazawa because Nakazawa states “the connectability and the heat dissipation can be enhanced at the same time”.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), and in further view of Lee et al. (US 20240107666 A1) and Nakazawa et al. (US 20140174795 A1)
Regarding Claim 13 – Kubo in view of Len teaches the circuit board according to claim 1, but does not explicitly disclose wherein the first through via has a diameter of 0.25 mm or less, and wherein the second through via has a diameter of 0.3 mm.
Lee teaches the first through via has a diameter of 0.25 mm or less (Figs 3-4; through hole 40; Lee [0020] states “the diameter of the through hole 40 is 0.1 mm”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len with the first through via has a diameter of 0.25 mm or less as taught by Lee because Lee teaches that using defined through hole structure increases contact area and improves electrical connection stability (Lee [0022]).
Nakazawa teaches the second through via has a diameter of 0.3 mm (Fig 1A; through hole 121; Nakazawa [0068] states “The diameter of the through hole 121 was set at 0.3 mm”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len with the second through via has a diameter of 0.3 mm as taught by Nakazawa because Nakazawa teaches a thermal via board in which “heat dissipation of the electronic component while enhancing the connectability of the heat transfer pattern with the heat sink of the electronic component”.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2), and in further view of Kobayashi et al. (US 20240023226 A1)
Regarding Claim 14 – Kubo in view of Len teaches the circuit board according to claim 1, but does not explicitly disclose an image forming apparatus comprising: a constituent part to be controlled by either one of the first electronic part or the second electronic part to form an image.
Kobayashi teaches an image forming apparatus (Figs 1-2; image forming apparatus 10) comprising: a constituent part to be controlled by either one of the first electronic part or the second electronic part to form an image (Figs 1-2; controller 11, scanner unit 12, printer unit 13, PCB 100, ICs 200, 201; Kobayashi [0025] states “The printer unit 13 is a device configured to form an image on a sheet using input image data”, [0029] states “controller 11 configured to control entire operations of the image forming apparatus 10”, see also [0041-0043]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len with an image forming apparatus comprising: a constituent part to be controlled by either one of the first electronic part or the second electronic part to form an image. Because Kobayashi teaches that “controller 11 configured to control entire operations of the image forming apparatus 10” thereby teaching the use of a PCB mounted electronic part to control a constituent part such as the printer unit to form an image.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US 20150359102 A1) in view of Len et al. (US 10980127 B2) and in further view of Maja et al. (US 20200349984 A1)
Regarding Claim 15 – Kubo in view of Len teaches the circuit board according to claim 1, wherein the first electronic part that is mounted or mountable to the first mounting region is d first integrated circuit package (Kubo Figs 1, 3; SP1, 2; Kubo [0036-0037]), but does not explicitly disclose wherein the second electronic part that is mounted or mountable to the second mounting region is a second integrated circuit package.
Maja teaches the second electronic part that is mounted or mountable to the second mounting region is a second integrated circuit package (Fig 5; 502, 508, 510, 516, 518; Maja [0022-0023]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Kubo in view of Len with the second electronic part that is mounted or mountable to the second mounting region is a second integrated circuit package as taught by Maja because Maja [0024] states that the arrangement results in “shorter stub lengths and simplified wire routing”
Allowable Subject Matter
Claims 8-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Prosecution Insights