DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
4. Claims 10-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "predischarge transistor" in line10. There is insufficient antecedent basis for this limitation in the claim since the only previous reference was to a transistor, not a predischarge transistor.
Claim 11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: It is not clear if the “transistor” referenced the claim refers back to the transistor or predischarge transistor recited by claim 10.
Claims 12-17 are dependent on claim 11 and do not cure its deficiency. therefore they are rejected on the same basis.
Double Patenting
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
6. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,074,992. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Patent contain every element of the claims of the instant application and as such anticipate the claims of the instant application.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
7. The following table shows the correspondence between the claims of the U.S. Patent and the instant application. Differences in language are bolded.
U.S. Patent 12,074,992
Application Ser. No. 18/790,296
1. A physical unclonable function (PUF) generator comprising: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row; and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to allow each of the plurality of bit cells to have a first metastable logical state; stabilize the first metastable logical state of each of the plurality of bit cells to a second logical state; determine the second logical state of each of the plurality of bit cells; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature, wherein each of the plurality of bit cells comprises at least one enable transistor, at least one access transistor, and at least one storage node.
1. A physical unclonable function (PUF) generator comprising: a PUF cell array comprising a plurality of bit cells; and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to transition each of the plurality of bit cells from a first metastable logical state to a second logical state, determine the second logical state of each of the plurality of bit cells, and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature, wherein each of the plurality of bit cells comprises at least one enable transistor, at least one access transistor, and at least one storage node.
2. The PUF generator of claim 1, further comprising at least one pre-discharge transistor coupled to each of the plurality of columns wherein each of the at least one pre-discharge transistor is coupled between the BL and a first voltage.
2. The PUF generator of claim 1, further comprising at least one pre-discharge transistor coupled to each of the plurality of bit cells.
3. The PUF generator of claim 2, wherein the at least one access transistor comprises an n-type metal oxide semiconductor (NMOS) transistor and the at least one enable transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.
7. The PUF generator of claim 1, wherein the at least one access transistor comprises an n-type metal oxide semiconductor (NMOS) transistor and the at least one enable transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.
4. The PUF generator of claim 2, wherein the at least one enable transistor is coupled between two cross-coupled inverters and a second voltage.
8. The PUF generator of claim 1, wherein the at least one enable transistor is coupled between two cross-coupled inverters.
5. The PUF generator of claim 2, wherein the at least one pre-discharge transistors is coupled between the BL and the first voltage.
5. The PUF generator of claim 2, wherein the at least one pre-discharge transistor is coupled between a bitline and a first voltage.
6. The PUF generator of claim 2, wherein the plurality of bit cells each further comprises two cross-coupled inverters each comprising one n-type metal oxide semiconductor (NMOS) and one p-type metal oxide semiconductor (PMOS) transistors.
3. The PUF generator of claim 2, wherein the plurality of bit cells each further comprises two cross-coupled inverters each comprising one n-type metal oxide semiconductor (NMOS) and one p-type metal oxide semiconductor (PMOS) transistors.
7. The PUF generator of claim 2, wherein the PUF control circuit is configured to turn on the at least one pre-discharge transistor and the at least one access transistor, and to turn off the at least one enable transistor to disable the two cross-coupled inverters to write the first metastable logical state to each of the plurality of bit cells.
4. The PUF generator of claim 3, wherein the PUF control circuit is configured to turn on the at least one pre-discharge transistor and the at least one access transistor, and to turn off the at least one enable transistor to disable the two cross-coupled inverters to write the first metastable logical state to each of the plurality of bit cells.
8. The PUF generator of claim 2, wherein the PUF control circuit is configured to turn on the at least one enable transistor, and turn off the at least one access transistor and the at least one pre-discharge transistor of each of the plurality of columns to allow the first metastable logical state to stabilize to the second logical state in each of the plurality of bit cells.
6. The PUF generator of claim 2, wherein the PUF control circuit is configured to turn on the at least one enable transistor, and turn off the at least one access transistor and the at least one pre-discharge transistor to allow the first metastable logical state to stabilize to the second logical state in each of the plurality of bit cells.
9. The PUF generator of claim 2, wherein the PUF control circuit is further configured to turn on the at least one access transistor to readout the second logical state from each of the plurality of bit cells to generate a PUF signature.
9. The PUF generator of claim 1, wherein the PUF control circuit is further configured to turn on the at least one access transistor to readout the second logical state from each of the plurality of bit cells to generate a PUF signature.
10. A method for generating a physical unclonable function (PUF) signature comprising: pre-charging at least one storage node with a predetermined voltage in each of a plurality of bit cells in a plurality of columns and at least one row of a PUF cell array by turning on at least one pre-discharge transistor coupled to each of the plurality of columns allowing each of the plurality of bit cells to have a first metastable logical state, wherein the at least one pre-discharge transistor is further coupled to a second voltage; stabilizing the first metastable logical state in each of the plurality of bit cells to a second logical state; and generating a PUF signature by reading out the second logical states of the plurality of bit cells.
10. A method for generating a physical unclonable function (PUF) signature comprising: pre-charging at least one storage node with a predetermined voltage in each of a plurality of bit cells in a PUF cell array by turning on at least one transistor coupled to each of the plurality of bit cells to have a first metastable logical state, wherein the at least one pre-discharge transistor is further coupled to a second voltage; stabilizing the first metastable logical state in each of the plurality of bit cells to a second logical state; and generating a PUF signature by reading out the second logical states of the plurality of bit cells.
11. The method of claim 10, wherein each of the plurality of bit cells comprises at least one enable transistor, at least one access transistor, and at least one storage node, wherein the at least one storage node of each of the plurality of bit cells in each of the plurality of columns are coupled to the at least one pre-discharge transistor of the corresponding column through the corresponding at least one access transistor, and wherein the pre-charging further comprises: turning on the at least one access transistor, and tuning off the at least one enable transistor.
11. The method of claim 10, wherein each of the plurality of bit cells comprises at least one enable transistor, at least one access transistor, and at least one storage node, wherein the at least one storage node of each of the plurality of bit cells are coupled to the at least one transistor through the corresponding at least one access transistor, and wherein the pre-charging further comprises: turning on the at least one access transistor, and tuning off the at least one enable transistor.
12. The method of claim 11, wherein the at least one access transistor is coupled between a bitline (BL) and one corresponding storage node.
12. The method of claim 11, wherein the at least one access transistor is coupled between a bitline (BL) and one corresponding storage node.
13. The method of claim 11, wherein the at least one access transistor comprises an n-type metal oxide semiconductor (NMOS) transistor and the at least one enable transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.
13. The method of claim 11, wherein the at least one access transistor comprises an n-type metal oxide semiconductor (NMOS) transistor and the at least one enable transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.
14. The method of claim 11, wherein the at least one enable transistor is coupled between two cross-coupled inverters and a first voltage.
14. The method of claim 11, wherein the at least one enable transistor is coupled between two cross-coupled inverters and a first voltage.
15. The method of claim 11, wherein the at least one pre-discharge transistor is coupled between the BL and the second voltage.
15. The method of claim 11, wherein the at least one pre-discharge transistor is coupled between the BL and the second voltage.
16. The method of claim 11, wherein the plurality of bit cells each further comprises two cross-coupled inverters each comprising one n-type metal oxide semiconductor (NMOS) and one p-type metal oxide semiconductor (PMOS) transistors.
16. The method of claim 11, wherein the plurality of bit cells each further comprises two cross-coupled inverters each comprising one n-type metal oxide semiconductor (NMOS) and one p-type metal oxide semiconductor (PMOS) transistors.
17. The method of claim 11, wherein the stabilizing and the generating further comprising: turning off the at least one pre-discharge transistor
17. The method of claim 11, wherein the stabilizing and the generating further comprising: turning off the at least one transistor.
18. A physical unclonable function (PUF) generator comprising: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least one pre-discharge transistor, and each of the plurality of bit cells comprises at least one storage node, wherein the at least one storage node of each of the plurality of bit cells in each of the plurality of columns are coupled to the at least one pre-discharge transistor of the corresponding column, wherein the at least one pre-discharge transistor is further coupled to a first voltage; and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least one storage node with substantially the same voltages allowing each of the plurality of bit cell to have a first metastable logical state; stabilize the first metastable logical state of each of the plurality of bit cells to a second logical state; determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.
18. A physical unclonable function (PUF) generator comprising: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells is coupled to at least one pre-discharge transistor, and each of the plurality of bit cells comprises at least one storage node, wherein the at least one storage node of each of the plurality of bit cells are coupled to the at least one pre-discharge transistor, wherein the at least one pre-discharge transistor is further coupled to a first voltage; and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least one storage node to place each of the plurality of bit cells in a first metastable logical state, stabilize the first metastable logical state of each of the plurality of bit cells to a second logical state, determine the second logical state of each of the plurality of bit cells, and based on the determined second logical states of the plurality of bit cells, generate a PUF signature.
19. The PUF generator of claim 18, wherein the at least one pre-discharge transistor is coupled between a bitline (BL) and the first voltage.
19. The PUF generator of claim 18, wherein the at least one pre-discharge transistor is coupled between a bitline (BL) and the first voltage.
20. The PUF generator of claim 18, wherein each of the plurality of bit cells further comprises at least one enable transistor, at least one access transistor, and two cross-coupled inverters, the PUF control circuit is configured to turn on the at least one pre-discharge transistor and the at least one access transistor and to turn off the at least one enable transistor to disable the two cross-coupled inverters to write the first metastable logical state to each of the plurality of bit cells.
20. The PUF generator of claim 18, wherein each of the plurality of bit cells further comprises at least one enable transistor, at least one access transistor, and two cross-coupled inverters, the PUF control circuit is configured to turn on the at least one pre-discharge transistor and the at least one access transistor and to turn off the at least one enable transistor to disable the two cross-coupled inverters to write the first metastable logical state to each of the plurality of bit cells.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Trimburger 9,608,827: Trimburger discloses a PUF generator circuit that includes a PUF control circuit having many of the same circuit elements of the instant application and operating to generate a PUF value based on differences in metastable states similarly to the instant application (see esp. col. 1 line 61 through col. 2 line 19).
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Paul E. Callahan whose telephone number is (571) 272-3869. The examiner presently works a part-time schedule and can normally be reached from 9am to 5pm on the first Monday and Tuesday and the second Thursday and Friday of the USPTO bi-week schedule.
The examiner’s email address is: Paul.Callahan1@USPTO.GOV
If attempts to reach the examiner by telephone are unsuccessful, the Examiner's supervisor, Alexander Lagor, can be reached on (571) 270-5143. The fax phone number for the organization where this application or proceeding is assigned is: (571) 273-8300.
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/PAUL E CALLAHAN/Examiner, Art Unit 2437