Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informality:
The related applications in the first paragraph of the specification should be updated as to their application status.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12, 15 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 12, line 2, “one corresponding storage node” is unclear and confusing as to whether it is part of the “at least one storage node” of claim 11 or an additional storage node.
In claim 15, line 2, “the BL” lacks proper antecedent basis.
In claim 17, line 2, “the at least one transistor” is unclear and confusing as to which transistor it is referring.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,074,992 for the reasons set forth in the Office Action dated March 4, 2026.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 6, 7, 5, 8, 3, 4 and 9-20, respectively, of U.S. Patent No. 11,811,953 since the corresponding claims of the instant application are anticipated by the corresponding identified claims in the patent.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 (meets claims 1 and 2 of the instant application), 6, 7, 5, 8, 3, 4 and 9-20, respectively, of U.S. Patent No. 10,880,102 since the corresponding claims of the instant application are anticipated by the corresponding identified claims in the patent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-10 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yabuuchi et al (U.S. Patent Publication 2015/0029784).
Regarding claim 1, Yabuuchi teaches in Figures 3 and 12 a physical unclonable function (PUF) generator comprising: a PUF cell array (300) comprising a plurality of bit cells (M); and a PUF control circuit (304) coupled to the PUF cell array, wherein the PUF control circuit is configured to transition each of the plurality of bit cells from a first metastable logical state to a second logical state (See paragraph [0158], “the potentials of the common read bit lines CTR and CBR as the inputs (IO1, IO2) of the sense amplifier circuit are in a state of being precharged”, “the sense amplifier circuit changes to a state according to variations in characteristics of the P-MOSFETs P9 and P10 and the N-MOSFETs N9 and N10”, “the potential difference between the input/output nodes IO1 and IO2 is amplified by positive feedback of the latch circuit configured with the inverter circuits, and a stable state is obtained”), determine the second logical state of each of the plurality of bit cells, and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature (Paragraph [0158], “the generated unique ID is transferred..”), wherein each of the plurality of bit cells comprises at least one enable transistor (P5-P7), at least one access transistor (N11), and at least one storage node (IO1, IO2).
Regarding claim 2, Yabuuchi further shows in Figure 12 at least one pre-discharge transistor (P3, P4) coupled to each of the plurality of bit cells.
Regarding claim 3, Yabuuchi further shows in Figure 12 the plurality of bit cells each further comprises two cross-coupled inverters (P9, N9, P10, N10) each comprising one n-type metal oxide semiconductor (NMOS) and one p-type metal oxide semiconductor (PMOS) transistors.
Regarding claim 5, Yabuuchi further shows in Figure 12 wherein the at least one pre-discharge transistor is coupled between a bitline and a first voltage.
Regarding claim 7, Yabuuchi further shows in Figure 12 wherein the at least one access transistor comprises an n-type metal oxide semiconductor (NMOS) transistor and the at least one enable transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.
Regarding claim 8, Yabuuchi further shows in Figure 12 wherein the at least one enable transistor is coupled between two cross-coupled inverters.
Regarding claim 9, Yabuuchi further teaches in paragraph [0158] wherein the PUF control circuit is further configured to turn on the at least one access transistor to readout the second logical state from each of the plurality of bit cells to generate a PUF signature.
Regarding claim 10, Yabuuchi further teaches a method for generating a physical unclonable function (PUF) signature comprising: pre-charging (Figure 10C, bit line pair BL is precharged) at least one storage node with a predetermined voltage in each of a plurality of bit cells in a PUF cell array by turning on at least one pre-discharge transistor (N7,N8) coupled to each of the plurality of bit cells to have a first metastable logical state, wherein the at least one pre-discharge transistor is further coupled to a second voltage (WL); stabilizing the first metastable logical state in each of the plurality of bit cells to a second logical state; and generating a PUF signature (ID Generation) by reading out the second logical states of the plurality of bit cells.
Regarding claims 18-20, Yabuuchi further shows in Figure 12 all the features as set forth above.
Allowable Subject Matter
Upon filing a Terminal Disclaimer and amending the claims to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action, claims 4, 6 and 11-17 would be allowable if claims 4, 6 and 11 were rewritten in independent form including all of the limitations of their base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM R KORZUCH whose telephone number is (571)272-7589. The examiner can normally be reached Mon.-Fri. 8:00-4:00.
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/WILLIAM R KORZUCH/Supervisory Patent Examiner, Art Unit 2491
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