Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajiki (US 8106495), in view of Pagaila (US 20090261466).
Regarding claim 1, Kajiki discloses a circuit module comprising:
an upper circuit board (substrate 50, Fig. 5) having a first upper main surface and a first lower main surface arranged in an up-down direction;
a lower circuit board (substrate 10) having a second upper main surface and a second lower main surface arranged in the up-down direction, the lower circuit board being located below the upper circuit board and overlapping the upper circuit board when viewed in the up-down direction;
one or more first solder balls (external connection terminal 78 is a solder balls; column 8, lines 29 – 30) and provided on the second lower main surface;
one or more second solder balls (solder ball 62 or 62x; column 7, line 3 - 7) each having an ellipsoidal shape (ellipsoidal shape of the connection ball 240, Fig. 1; or 62, Fig. 5), located in an inter-board region between the upper circuit board and the lower circuit board, and electrically connecting the upper circuit board and the lower circuit board,
the second solder balls having a maximum width in a direction orthogonal to the up-down direction larger than a maximum width of the first solder balls in the direction orthogonal to the up-down direction (the ball 240 is larger than the ball 280; Fig. 1C. The all 62 is larger than the ball 78); and
a first sealing resin (the molding resin 76) provided in the inter-board region so as to be in contact with the first lower main surface and the second upper main surface and cover surfaces of the one or more second solder balls.
Kajiki does not explicitly disclose one or more first solder balls each having an ellipsoidal shape.
Pagaila teaches the solder balls (156, Fig. 5) having ellipsoidal shape.
It would have been obvious to one having skill in the art at the effective filing date of the invention adjust the shape of the components in order to fit all the components on the limited space of the electronic device.
Claim(s) 2, 5, 6, 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajiki (US 8106495), in view of Pagaila (US 20090261466), in further view of Mohammed (US 20050035440).
Regarding claim 2, Kajiki discloses the claimed invention as set forth in claim 1.
Kajiki does not explicitly disclose the circuit module further includes a second sealing resin covering the first upper main surface.
Mohammed suggests a second sealing resin (1004, Fig. 10) covering the first upper main surface (1016).
It would have been obvious to one having skill in the art at the effective filing date of the invention to add the sealing resin in order to protect the component on the surface of the circuit board from environment.
Regarding claim 5, Kajiki discloses the claimed invention as set forth in claim 1.
Kajiki does not explicitly disclose the circuit module further includes a third sealing resin covering the second lower main surface.
Mohammed teaches the third sealing resin added as needed, Fig. 3A.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more resin layer as needed in order to protect the components from the environment.
Regarding claim 6, Kajiki discloses the claimed invention as set forth in claim 5. Pagaila further suggests the one or more first solder balls each have a bottom surface being a plane orthogonal to the up-down direction (Fig. 5), and wherein the bottom surface of each of the one or more first solder balls is included in one plane together with a lower main surface of the third sealing resin (third resin was suggested by Mohammed in claim 5).
Regarding claim 10, Kajiki discloses the claimed invention as set forth in claim 2.
Kajiki does not explicitly disclose the circuit module further includes a third sealing resin covering the second lower main surface.
Mohammed teaches the third sealing resin added as needed, Fig. 3A.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more resin layer as needed in order to protect the components from the environment.
Regarding claim 11, Kajiki discloses the claimed invention as set forth in claim 3.
Kajiki does not explicitly disclose the circuit module further includes a third sealing resin covering the second lower main surface.
Mohammed teaches the third sealing resin added as needed, Fig. 3A.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more resin layer as needed in order to protect the components from the environment.
Claim(s) 7, 13 - 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajiki (US 8106495), in view of Pagaila (US 20090261466), in further view of Marimuthu (US 20100133704).
Regarding claim 7, Kajiki discloses the claimed invention as set forth in claim 1.
Kajiki further discloses the one or more second solder balls (62) are in contact with a mounting electrode (60) of the upper circuit board and a mounting electrode of the lower circuit board (20).
Kajiki does not explicitly disclose one or more first electronic components mounted on the first lower main surface; and one or more second electronic components mounted on the second upper main surface, wherein the one or more second electronic components do not overlap the one or more first electronic components when viewed in the up-down direction.
Marimuthu teaches one or more first electronic components (the die 440, Fig. 8i) mounted on the first lower main surface; and one or more second electronic components (the die 406) mounted on the second upper main surface, wherein the one or more second electronic components (406) do not overlap the one or more first electronic components (440) when viewed in the up-down direction.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more electronic component into the circuit board in order to form the intended circuitry.
Regarding claim 13, Kajiki discloses the claimed invention as set forth in claim 2.
Kajiki further discloses the one or more second solder balls (62) are in contact with a mounting electrode (60) of the upper circuit board and a mounting electrode of the lower circuit board (20).
Kajiki does not explicitly disclose one or more first electronic components mounted on the first lower main surface; and one or more second electronic components mounted on the second upper main surface, wherein the one or more second electronic components do not overlap the one or more first electronic components when viewed in the up-down direction.
Marimuthu teaches one or more first electronic components (the die 440, Fig. 8i) mounted on the first lower main surface; and one or more second electronic components (the die 406) mounted on the second upper main surface, wherein the one or more second electronic components (406) do not overlap the one or more first electronic components (440) when viewed in the up-down direction.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more electronic component into the circuit board in order to form the intended circuitry.
Regarding claim 14, Kajiki discloses the claimed invention as set forth in claim 3.
Kajiki further discloses the one or more second solder balls (62) are in contact with a mounting electrode (60) of the upper circuit board and a mounting electrode of the lower circuit board (20).
Kajiki does not explicitly disclose one or more first electronic components mounted on the first lower main surface; and one or more second electronic components mounted on the second upper main surface, wherein the one or more second electronic components do not overlap the one or more first electronic components when viewed in the up-down direction.
Marimuthu teaches one or more first electronic components (the die 440, Fig. 8i) mounted on the first lower main surface; and one or more second electronic components (the die 406) mounted on the second upper main surface, wherein the one or more second electronic components (406) do not overlap the one or more first electronic components (440) when viewed in the up-down direction.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more electronic component into the circuit board in order to form the intended circuitry.
Regarding claim 15, Kajiki discloses the claimed invention as set forth in claim 4.
Kajiki further discloses the one or more second solder balls (62) are in contact with a mounting electrode (60) of the upper circuit board and a mounting electrode of the lower circuit board (20).
Kajiki does not explicitly disclose one or more first electronic components mounted on the first lower main surface; and one or more second electronic components mounted on the second upper main surface, wherein the one or more second electronic components do not overlap the one or more first electronic components when viewed in the up-down direction.
Marimuthu teaches one or more first electronic components (the die 440, Fig. 8i) mounted on the first lower main surface; and one or more second electronic components (the die 406) mounted on the second upper main surface, wherein the one or more second electronic components (406) do not overlap the one or more first electronic components (440) when viewed in the up-down direction.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more electronic component into the circuit board in order to form the intended circuitry.
Regarding claim 16, Kajiki discloses the claimed invention as set forth in claim 5.
Kajiki further discloses the one or more second solder balls (62) are in contact with a mounting electrode (60) of the upper circuit board and a mounting electrode of the lower circuit board (20).
Kajiki does not explicitly disclose one or more first electronic components mounted on the first lower main surface; and one or more second electronic components mounted on the second upper main surface, wherein the one or more second electronic components do not overlap the one or more first electronic components when viewed in the up-down direction.
Marimuthu teaches one or more first electronic components (the die 440, Fig. 8i) mounted on the first lower main surface; and one or more second electronic components (the die 406) mounted on the second upper main surface, wherein the one or more second electronic components (406) do not overlap the one or more first electronic components (440) when viewed in the up-down direction.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more electronic component into the circuit board in order to form the intended circuitry.
Regarding claim 17, Kajiki discloses the claimed invention as set forth in claim 6.
Kajiki further discloses the one or more second solder balls (62) are in contact with a mounting electrode (60) of the upper circuit board and a mounting electrode of the lower circuit board (20).
Kajiki does not explicitly disclose one or more first electronic components mounted on the first lower main surface; and one or more second electronic components mounted on the second upper main surface, wherein the one or more second electronic components do not overlap the one or more first electronic components when viewed in the up-down direction.
Marimuthu teaches one or more first electronic components (the die 440, Fig. 8i) mounted on the first lower main surface; and one or more second electronic components (the die 406) mounted on the second upper main surface, wherein the one or more second electronic components (406) do not overlap the one or more first electronic components (440) when viewed in the up-down direction.
It would have been obvious to one having skill in the art at the effective filing date of the invention to add more electronic component into the circuit board in order to form the intended circuitry.
Allowable Subject Matter
Claims 3 – 4, 8, 9, 11, 12, 18 - 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 3, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the circuit module further includes a shield conductor covering an upper surface of the second sealing resin, a side surface of the second sealing resin located in the direction orthogonal to the up-down direction, a side surface of the upper circuit board located in the direction orthogonal to the up-down direction, a side surface of the first sealing resin located in the direction orthogonal to the up-down direction, and a side surface of the lower circuit board located in the direction orthogonal to the up-down direction. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 8, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the circuit module includes: one or more second electronic components mounted on the second upper main surface; and one or more via hole conductors having a frustum shape having a central axis extending in the up-down direction, located in the inter-board region between the upper circuit board and the lower circuit board, and electrically connecting the upper circuit board and the lower circuit board, wherein the one or more second solder balls are in contact with a mounting electrode of the lower circuit board, wherein the one or more via hole conductors are in contact with a mounting electrode of the upper circuit board, and wherein the one or more second solder balls and the one or more via hole conductors are arranged in the up-down direction and are in contact with each other. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 9, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the circuit module includes: one or more first electronic components mounted on the first lower main surface; one or more second electronic components mounted on the second upper main surface; and one or more third solder balls each having an ellipsoidal shape, located in the inter-board region between the upper circuit board and the lower circuit board, and electrically connecting the upper circuit board and the lower circuit board, wherein at least one of the one or more first electronic components overlaps at least one of the one or more second electronic components when viewed in the up-down direction, wherein the one or more second solder balls are in contact with a mounting electrode of the lower circuit board, wherein the one or more third solder balls are in contact with a mounting electrode of the upper circuit board, and wherein the one or more second solder balls and the one or more third solder balls are arranged in the up-down direction and are in contact with each other. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 18, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 & 2, a combination of limitations that the circuit module includes: one or more second electronic components mounted on the second upper main surface; and one or more via hole conductors having a frustum shape having a central axis extending in the up-down direction, located in the inter-board region between the upper circuit board and the lower circuit board, and electrically connecting the upper circuit board and the lower circuit board, wherein the one or more second solder balls are in contact with a mounting electrode of the lower circuit board, wherein the one or more via hole conductors are in contact with a mounting electrode of the upper circuit board, and wherein the one or more second solder balls and the one or more via hole conductors are arranged in the up-down direction and are in contact with each other. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 20170117214) discloses two substrate coupled to each other having electronic components, and solder balls, Fig. 7.
Nishimura (US 6781241) discloses two substrate having solder balls, and electronic components in between, Fig. 2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BINH B TRAN/Primary Examiner, Art Unit 2847
Prosecution Insights