DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 31, 2024 has been considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on February 25, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 6-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakano (US 2013/0306983 A1).
Claim 1, Nakano discloses a silicon carbide semiconductor device (MIS transistor 1/81 is a trench gate semiconductor device in which SiC is employed, hereinafter, silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10), comprising:
a semiconductor substrate containing silicon carbide (SiC substrate 5 and SiC epitaxial layer 8 are a semiconductor substrate containing silicon carbide, hereinafter, semiconductor substrate 5/8, [0086], Fig. 10), the semiconductor substrate 5/8 having a first main surface (front surface 9 is a first main surface, hereinafter, first main surface 9, [0087], Fig. 10) and a second main surface (rear surface 7 is a second main surface, hereinafter, second main surface 7, [0087], Fig. 10) opposite to each other (first main surface 9 and second main surface 7 are opposite to each other on the semiconductor substrate 5/8, [0087], Fig. 10);
a first semiconductor region (n- type low-concentration region 83 and n-type high-concentration region 84 form the drift region 82 which is a first semiconductor region, hereinafter, first semiconductor region 82, [0151], Fig. 10) of a first conductivity type (first semiconductor region 82 is n type, hereinafter, first semiconductor region 82 of a first conductivity type (i.e. n-type), [0151], Fig. 10), provided in the semiconductor substrate 5/8 (first semiconductor region 82 of a first conductivity type (i.e. n-type) is provided in the semiconductor substrate 5/8, [0151], Fig. 10);
a second semiconductor region (source breakdown voltage holding regions 28 and body regions 12 form a second semiconductor region, hereinafter, second semiconductor region 12/28, [0103], Fig. 10) of a second conductivity type (second semiconductor region 12/28 are p type, hereinafter, second semiconductor region 12/28 of a second conductivity type (i.e. p-type), [0089] and [0103], Fig. 10), provided in the semiconductor substrate 5/8 between the first main surface 9 of the semiconductor substrate 5/8 and the first semiconductor region 83 (second semiconductor region 12/28 of a second conductivity type (i.e. p-type) is provided between the first main surface 9 of the semiconductor substrate 5/8 and the first semiconductor region 83 within the semiconductor substrate 5/8, [0089] and [0103], Fig. 10);
a third semiconductor region (source regions 14 is a third semiconductor region, hereinafter, third semiconductor region 14, [0091], Fig. 10) of the first conductivity type (third semiconductor region 14 is n type, hereinafter, third semiconductor region 14 of the first conductivity type (i.e. n-type), [0091], Fig. 10), selectively provided in the semiconductor substrate 5/8 between the first main surface 9 of the semiconductor substrate 5/8 and the second semiconductor region 12/28 (third semiconductor region 14 of the first conductivity type (i.e. n-type) is selectively provided in the semiconductor substrate 5/8 between the first main surface 9 of the semiconductor substrate 5/8 and the second semiconductor region 12/28, [0091] and [0103], Fig. 10);
a first trench (gate trench 15 is a first trench, hereinafter, first trench 15¸ [0092], Fig. 10) penetrating through the third semiconductor region 14 and the second semiconductor region 12/28 in a depth direction (first trench 15 penetrates through the third semiconductor region 14 and the second semiconductor region 12/28 in a depth direction¸ [0092], Fig. 10) and terminating in the first semiconductor region 82 (first trench 15 penetrates through the third semiconductor region 14 and the second semiconductor region 12/28 in a depth direction and terminates in the first semiconductor region 82¸ [0092], Fig. 10);
a gate electrode (gate electrode 23, [0097], Fig. 10) provided in the first trench 15 (gate electrode 23 is provided in the first trench 15, [0097], Fig. 10), via a gate insulating film (gate electrode 23 is provided in the first trench 15 via a gate insulating film 22, [0095], Fig. 10);
a plurality of second trenches (source trenches 24 are a plurality of second trenches, hereinafter, plurality of second trenches 24, [0098], Fig. 10) penetrating through the third semiconductor region 14 in the depth direction and terminating in the second semiconductor region 12/28 (plurality of second trenches 24 penetrate through the third semiconductor region 14 in the depth direction and terminating in the second semiconductor region 12/28, [0098], Fig. 10), at a depth at least equal to a depth of the first trench 15 (plurality of second trenches 24 penetrate through the third semiconductor region 14 in the depth direction at a depth at least equal to a depth of the first trench 15, [0098], Fig. 10), the plurality of second trenches 24 being provided apart from the first trench 15 and a periphery of each of the plurality of second trenches 24 being bordered by the second semiconductor region 12/28 in a plan view of the silicon carbide semiconductor device 1/81 (the plurality of second trenches 24 being provided apart from the first trench 15 and a periphery of each of the plurality of second trenches 24 being bordered by the second semiconductor region 12/28 in a plan view of the silicon carbide semiconductor device 1/81, [0103], Fig. 10);
a fourth semiconductor region (first semiconductor region 82 includes the n- type low-concentration region 83 and n-type high-concentration region 84, however, the n-type high-concentration region 84 within the first semiconductor region 82 may form the fourth semiconductor region, hereinafter, fourth semiconductor region 84, [0151], Fig. 10) of the first conductivity type (i.e. n-type) (fourth semiconductor region 84 is n type, hereinafter, fourth semiconductor region 84 of the first conductivity type (i.e. n-type), [0151], Fig. 10), provided opposing, in the depth direction, a portion of the second semiconductor region 12/28 that is below a bottom of each of the plurality of second trenches 24 (fourth semiconductor region 84 of the first conductivity type (i.e. n-type) is provided opposing, in the depth direction, a portion of the second semiconductor region 12/28 that is below a bottom of each of the plurality of second trenches 24, [0151], Fig. 10), the fourth semiconductor region 84 having a doping concentration higher than a doping concentration of the first semiconductor region 83 (fourth semiconductor region 84 having a doping concentration (i.e. high-concentration region 84, 2 x 1015 to 1 x 1018 cm-3) higher than a doping concentration of the first semiconductor region 83 (i.e. low-concentration region 83, 1 x 1015 to 1 x 1017 cm-3), [0151], Fig. 10);
a first electrode (source electrode 37 is a first electrode, hereinafter, first electrode 37, [0109], Fig. 10) provided at the first main surface 9 of the semiconductor substrate 5/8 (first electrode 37 is provided at the first main surface 9 of the semiconductor substrate 5/8, [0109], Fig. 10), embedded in the plurality of second trenches 24 (first electrode 37 is embedded in the plurality of second trenches 24, [0109], Fig. 10), the first electrode 37 being in contact with the second semiconductor region 12/28 and the third semiconductor region 14 at an inner wall of each of the plurality of second trenches 24 (first electrode 37 is in contact with the second semiconductor region 12/28 and the third semiconductor region 14 at an inner wall of each of the plurality of second trenches 24, [0109], Fig. 10); and
a second electrode (drain electrode 38 is a second electrode, hereinafter, second electrode 38, [0112], Fig. 10) provided at the second main surface 7 of the semiconductor substrate 5/8 (second electrode 38 is provided at the second main surface 7 of the semiconductor substrate 5/8, [0112], Fig. 10).
Claim 4, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 1.
Nakano discloses wherein the fourth semiconductor region 84 is provided spanning an entire area between the second semiconductor region 12/28 and the first semiconductor region 83 (fourth semiconductor region 84 is provided spanning an entire area between the second semiconductor region 12/28 and the first semiconductor region 83, [0151], Fig. 10), and
the fourth semiconductor region 84 further opposes, in the depth direction, a bottom of the first trench 15 (fourth semiconductor region 84 further opposes, in the depth direction, a bottom of the first trench 15, [0154], Fig. 10).
Claim 6, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 4.
Nakano discloses wherein the fourth semiconductor region 84 is apart from the bottom of the first trench 15 (fourth semiconductor region 84 is apart from the bottom of the first trench 15, [0154], Fig. 10).
Claim 7, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 6.
Nakano discloses wherein a thickness of the fourth semiconductor region 84 is constant over a portion thereof facing the bottom of the first trench 15 and bottoms of the plurality of second trenches 24 (a thickness of the fourth semiconductor region 84 is constant over a portion thereof facing the bottom of the first trench 15 and bottoms of the plurality of second trenches 24, [0098], Fig. 10).
Claim 8, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 1.
Nakano discloses wherein the fourth semiconductor region 84 is in contact with said portion of the second semiconductor region 12/28 (fourth semiconductor region 84 is in contact with said portion of the second semiconductor region 12/28, [0098], Fig. 10).
Claim 9, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 1.
Nakano discloses wherein a bottom of the first trench 15 is bordered by the first semiconductor region 83 (a bottom of the first trench 15 is bordered by the first semiconductor region 83, [0152], Fig. 10).
Claim 10, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 1.
Nakano discloses wherein the plurality of second trenches 24 is disposed with a predetermined interval in a direction parallel to the first main surface 9 of the semiconductor substrate 5/8 (plurality of second trenches 24 is disposed with a predetermined interval in a direction parallel to the first main surface 9 of the semiconductor substrate 5/8, [0087], Fig. 10), and
the first trench 15 is disposed in plural at a predetermined pitch in the direction, each between adjacent two of the plurality of second trenches 24 (first trench 15 is disposed in plural at a predetermined pitch in the direction, each between adjacent two of the plurality of second trenches 24, [0087, Fig. 10).
Claim 11, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 1.
Nakano discloses further comprising a plurality of first trenches that each is said first trench 15, wherein the plurality of first trenches 15 and the plurality of second trenches 24 are so arranged that each of the plurality of second trenches 24 has, respectively on two sides thereof (a plurality of first trenches that each is said first trench 15, wherein the plurality of first trenches 15 and the plurality of second trenches 24 are so arranged that each of the plurality of second trenches 24 has, respectively on two sides thereof, [0154], Fig. 10),
one of the plurality of first trenches 15, provided separately from said each second trench 24 (one of the plurality of first trenches 15, provided separately from said each second trench 24, [0154], Fig. 10), and
another one of the plurality of second trenches 24, provided separately from said each second trench 24 (another one of the plurality of second trenches 24, provided separately from said each second trench 24, [0154], Fig. 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Nakagawa (US 2020/0243641 A1).
Claim 2, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 1.
Nakano does not explicitly disclose further comprising a fifth semiconductor region of the first conductivity type (i.e. n-type), provided opposing, in the depth direction, a bottom of the first trench, the fifth semiconductor region having a doping concentration higher than the doping concentration of the first semiconductor region.
However, Nakagawa (US 2020/0243641 A1) discloses further comprising a fifth semiconductor region of the first conductivity type (i.e. n-type), provided opposing, in the depth direction, a bottom of the first trench 15 (Nakagawa, high concentration region 112a is a fifth semiconductor region 112a of the first conductivity type (i.e. n-type), hereinafter, fifth semiconductor region 112a of the first conductivity type (i.e. n-type), [0446], Fig. 13; Nakano, first trench 15¸ [0092], Fig. 10), the fifth semiconductor region having a doping concentration higher than the doping concentration of the first semiconductor region 83 (Nakagawa, fifth semiconductor region 112a of the first conductivity type (i.e. n-type) and has a doping concentration (i.e. high-concentration region 112a, 1 x 1016 to 1 x 1018 cm-3) higher than the doping concentration of the low concentration region 112b which is a first semiconductor region, hereinafter, first semiconductor region 112b (i.e. low-concentration region 112b, 1 x 1015 to 1 x 1016 cm-3), [0446], Fig. 13; Nakano, first semiconductor region 83 (i.e. low-concentration region 83, 1 x 1015 to 1 x 1017 cm-3), [0151], Fig. 10, [0151], Fig. 10). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of relative doping concentrations with respect to the above lying trench gate (result effective at least insofar as relative doping concentrations with respect to the above lying trench gate enables improving the short circuit withstand capability and reducing the feedback capacitance (Nakagawa, [0010])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed relative doping concentrations with respect to the above lying trench gate or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 3, Nakano/Nakagawa discloses the silicon carbide semiconductor device (Nakano, silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10; Nakagawa, semiconductor device 101 includes silicon carbide, hereinafter, silicon carbide semiconductor device 101, [0419], Fig. 13) according to claim 2.
Nakano/Nakagawa discloses wherein the doping concentration of the fifth semiconductor region is not more than the doping concentration of the fourth semiconductor region (Nakagawa, doping concentration of the fifth semiconductor region 112a of the first conductivity type (i.e. n-type) and has a doping concentration (i.e. high-concentration region 112a, 1 x 1016 to 1 x 1018 cm-3) is not more than the doping concentration of the fourth semiconductor region, [0446], Fig. 13; Nakano, fourth semiconductor region 84 of the first conductivity type (i.e. n-type) has a doping concentration (i.e. high-concentration region 84, 2 x 1015 to 1 x 1018 cm-3), [0151], Fig. 10).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of
Kyogoku (US 2021/0083101 A1).
Claim 5, Nakano discloses the silicon carbide semiconductor device (silicon carbide semiconductor device 1/81, [0083] and [0151], Fig. 10) according to claim 4.
Nakano does not explicitly disclose wherein the fourth semiconductor region is in contact with the gate insulating film, at the bottom of the first trench.
However, Kyogoku discloses wherein the fourth semiconductor region is in contact with the gate insulating film, at the bottom of the first trench (Kyogoku, n-type high concentration region 33 is a fourth semiconductor region, hereinafter, fourth semiconductor region 33 and is in contact with the gate insulating film 18, at the bottom of the first trench 21, [0050], Fig. 19; Nakano, fourth semiconductor region 84 is in electrical contact with the gate insulating film 22, at the bottom of the first trench 15). The combination to utilize a gate insulating film directly in contact with the underlying fourth semiconductor region would allow for the reliability of the gate insulating layer to be improved (Kyogoku, [0144]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a gate insulating film directly in contact with the underlying fourth semiconductor region to allow for the reliability of the gate insulating layer to be improved (Kyogoku, [0144]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sugahara (US 2018/0033876 A1) discloses a silicon carbide semiconductor device 100, comprising:
a semiconductor substrate 1 containing silicon carbide, the semiconductor substrate 1 having a first main surface and a second main surface opposite to each other;
a first semiconductor region of a first conductivity type 24, provided in the semiconductor substrate 1;
a second semiconductor region of a second conductivity type 17, provided in the semiconductor substrate 1 between the first main surface of the semiconductor substrate 1 and the first semiconductor region 24;
a third semiconductor region of the first conductivity type 8, selectively provided in the semiconductor substrate 1 between the first main surface of the semiconductor substrate 1 and the second semiconductor region 17;
a first trench 11 penetrating through the third semiconductor region 8 and the second semiconductor region 17 in a depth direction and terminating in the first semiconductor region 24;
a gate electrode 13 provided in the first trench 11, via a gate insulating film 12;
a first electrode 42 provided at the first main surface of the semiconductor substrate 1, the first electrode 42 being in contact with the second semiconductor region 17 and the third semiconductor region 8; and
a second electrode 25 provided at the second main surface of the semiconductor substrate 1.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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