Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed April 15th, 2026 has been entered. Claims 1-20 are pending in this application. Independent claims 1 and 15 have been amended. The amendment changing “target data rate” to “target code rate” has been considered. In view of the amendment and Applicant’s arguments, the prior art rejection previously set forth in the Non-Final Office Action mailed January 15th, 2026, has been revised. Accordingly, claims 1-20 are rejected under 35 USC § 103 as being unpatentable over Hedberg (US 2006/0218459), in view of Montorsi et al. (US 11,671,115), hereinafter Montorsi.
Response to Arguments
Applicant’s arguments, see pages 7-10, filed April 15th, 2026, with respect to the rejection(s) of claims 1-20 under 35 USC § 103, as being unpatentable over Ahn et al. (US 10,680,652), hereinafter Ahn, in view of Montorsi, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. Applicant argues that Ahn fails to teach or suggest selecting, based at least on a target code rate and abase code rate, a first size of information bits that is less than a base size of information bits, and further fails to teach generating a second set of information bits including the first set of information bits and one or more additional bits to increase the size of the second set of information bits to correspond to the base size of information bits. Applicant argues that Montorsi does not cure the alleged deficiencies of Ahn. However, upon further consideration and an update search, a new ground(s) of rejection is made, as set forth below.
As set forth in the rejection below, Hedberg teaches receiving and utilizing a target code rate, selecting a base code rate and base code block size, determining code block sizing, determining shortening parameters, updating base code words, and generating adaptive codeword lengths. Hedberg further teaches using fill bits, zero padding bits, shortening, and puncturing to adapt information blocks to selected code blocks. Montorsi teaches LDCP code construction having different LDPC code rates. Accordingly, the presently applied combination teaches or suggests the claimed determining of information bit sizes based on coding rates and generating information blocks corresponding to the selected base codes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hedberg, in view of Montorsi.
Regarding claim 1, Hedberg teaches an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a target code rate that has a base code rate for a base size of information bits (Hedberg, Fig. 4 teaches a target code rate 408 as input to a PPDU encoder 320; para. [0040], lines 8-12, “In conjunction with selecting a base code rate 418, the PPDU encoder 320 selects a base code block size (e.g., 648). That is, the PPDU encoder 320 preferably determines the optimal combination of longest block size and lowest rate”); select, based at least on the target code rate and the base code rate, a first size of information bits that is less than the base size of information bits (Hedberg, Fig. 9; para. [0042], lines 1-12, “the PPDU encoder 320 can select any available code rate that is lower than or equal to the target code rate 408, since the coding system 300 enables transmission of data at a lower code rate in the same amount of time as the target code rate. Thus, the PPDU encoder 320 is configured to adapt the code rate to produce a new base code rate and structure that is defined in terms of the codewords across all the OFDM symbols that are optimized for performance with a minimum number of wasted bits. The PPDU encoder 320 packs the codewords into the transmission frame and decides what rate to use and how many bits to use per code block”); generate a second set of information bits to include a first set of information bits corresponding to the first size of information bits and one or more bits to increase a size of the second set of information to correspond to the base size of information bits (Hedberg, Fig. 5E & 5F, bit region 509; para. [0057], lines 1-6, “With continued reference to FIGS. SE and SF, note bit region 509, which is referred to as a zero padding or fill bit region. PSDU s are generally encoded with zero pad bits or fill bits added as needed so that an integral number of code blocks and an integral number of OFDM symbols can be transmitted”; para. [0058], lines 1-3, “The zero padding region 509 can be filled with zero or useless bits in some embodiments, or replicated bits in some embodiments”); encode, using the base code rate, the second set of information bits (Hedberg, para. [0039], lines 15-20, “When a packet is to be transmitted, the MAC decides the modulation mode [e.g., modulation 406] and which of these basic rates to target [e.g., target code rate 408] in the transmission. The target code rate 408 is viewed as an upper bound for the actual rate used after PPDU encoding the data into a packet”; para. [0040], lines 8-12, “In conjunction with selecting a base code rate 418, the PPDU encoder 320 selects a base code block size (e.g., 648). That is, the PPDU encoder 320 preferably determines the optimal combination of longest block size and lowest rate”) to generate parity data; and generate a codeword by concatenating the first set of information bits and the parity data to achieve the target code rate (Hedberg, para. [0044], lines 11-16, “For instance, the encoder 320 receives information [e.g., target code rate 408] from the MAC requiring a coding rate, R, say of
2
3
. The PPDU encoder 320 is to theoretically construct a code block in a manner such that
2
3
of the final code block is payload data 502 and the remaining
1
3
are parity bits 504 used in the coding process”), wherein the transmitter is configured to transmit the codeword (Hedberg, Fig. 3 teaches a transmitter device 302).
Hedberg fails to explicitly teach identify a low density parity check (LDPC) code that has a base code rate for a base size of information bits.
However, Montorsi, in an analogous art, teaches identify a low density parity check (LDPC) code that has a base code rate for a base size of information bits (Montorsi, Figs. 5A-5D teaches partitioned LDPC parity check matrices having different LDPC code rates).
Hedberg and Montorsi are both considered to be analogous to the claimed invention because both are in the same field of LDPC error correction coding systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hedberg to incorporate the teachings of Montorsi by including the functionality of identifying LDPC codes having a base code rate for information bits.
The suggestion/motivation for doing so would be to allow for flexibility in achieving desired coding rates for transmitted data.
Regarding claim 2, the combination of Hedberg in view of Montorsi teaches the apparatus of claim 1, wherein the target code rate is smaller than the base code rate (Hedberg, para. [0042], lines 1-5, “the PPDU encoder 320 can select any available code rate that is lower than or equal to the target code rate 408, since the coding system 300 enables transmission of data at a lower code rate in the same amount of time as the target code rate”).
Regarding claim 3, the combination of Hedberg in view of Montorsi teaches the apparatus of claim 1, wherein in generating the second set of information bits, the one or more processors are configured to: determine, based at least on the target code rate and the base code rate, a second size of the one or more bits (Hedberg, Fig. 9 teaches determining minimum packet size, base code rate, number of cod bocks, and shortening, as well as updating the number of base code words and outputting adaptive codeword lengths); and generate the one or more bits corresponding to the second size of the one or more bits (Hedberg, para. [0057], lines 1-6, “With continued reference to FIGS. SE and SF, note bit region 509, which is referred to as a zero padding or fill bit region. PSDU s are generally encoded with zero pad bits or fill bits added as needed so that an integral number of code blocks and an integral number of OFDM symbols can be transmitted”; para. [0058], lines 1-3, “The zero padding region 509 can be filled with zero or useless bits in some embodiments, or replicated bits in some embodiments”).
Regarding claim 4, the combination of Hedberg in view of Montorsi teaches the apparatus of claim 1, wherein the one or more processors are further configured to: determine, based at least on a coded bit error rate or a frame error probability, a set of masked bits corresponding to the base size of information bits (Hedberg, para. [0060], lines 4-13, “Coded block structure 604 of FIG. 6B comprises the packet 602 broken down into minimum block sizes. In particular, the blocks shown comprise punctured and shortened (p-s) 648 bit blocks 606. In punctured code words, which was not shown in FIGS. 5A-5F, some of the encoded bits are systematically not transmitted. The decoder 330 fills in these missing or ‘erased’ bits in the decoding process. Puncturing effectively decreases the ratio of parity bits to transmitted bits and thus increases the effective code rate”; punctured bits equate to masked bits because they are intentionally omitted from transmission and are treated as missing or erased bits during decoding); generate, based at least on the set of masked bits and the second set of information bits, a third set of information bits (Hedberg, para. [0057], lines 1-6, “With continued reference to FIGS. SE and SF, note bit region 509, which is referred to as a zero padding or fill bit region. PSDU s are generally encoded with zero pad bits or fill bits added as needed so that an integral number of code blocks and an integral number of OFDM symbols can be transmitted”; para. [0058], lines 1-3, “The zero padding region 509 can be filled with zero or useless bits in some embodiments, or replicated bits in some embodiments”) corresponding to the base size of information bits (Hedberg, Fig. 9 teaches determining minimum packet size, base code rate, number of cod bocks, and shortening, as well as updating the number of base code words and outputting adaptive codeword lengths); encode, using the base code rate, the third set of information bits (Hedberg, para. [0039], lines 15-20, “When a packet is to be transmitted, the MAC decides the modulation mode [e.g., modulation 406] and which of these basic rates to target [e.g., target code rate 408] in the transmission. The target code rate 408 is viewed as an upper bound for the actual rate used after PPDU encoding the data into a packet”; para. [0040], lines 8-12, “In conjunction with selecting a base code rate 418, the PPDU encoder 320 selects a base code block size (e.g., 648). That is, the PPDU encoder 320 preferably determines the optimal combination of longest block size and lowest rate”) to generate second parity data (Hedberg, para. [0044], lines 11-16, “For instance, the encoder 320 receives information [e.g., target code rate 408] from the MAC requiring a coding rate, R, say of
2
3
. The PPDU encoder 320 is to theoretically construct a code block in a manner such that
2
3
of the final code block is payload data 502 and the remaining
1
3
are parity bits 504 used in the coding process”); and generate the codeword by concatenating the first set of information bits and the second parity data to achieve the target code rate (Hedberg, para. [0044], lines 11-16, “For instance, the encoder 320 receives information [e.g., target code rate 408] from the MAC requiring a coding rate, R, say of
2
3
. The PPDU encoder 320 is to theoretically construct a code block in a manner such that
2
3
of the final code block is payload data 502 and the remaining
1
3
are parity bits 504 used in the coding process”).
Regarding claim 5, the combination of Hedberg in view of Montorsi teaches the apparatus of claim 1, wherein the second set of information bits are encoded using the identified LDPC code to generate the parity data (Hedberg, para. [0026], lines 3-6, “The coding systems of the preferred embodiments comprise advanced forward error correction [FEC] coding features using low density parity check [LDPC] codes”).
Regarding claim 6, the combination of Hedberg in view of Montorsi teaches the apparatus of claim 1, wherein a ratio of the first size of information bits to a size of the codeword is equal to the target code rate (Hedberg, para. [0044], lines 11-16, “For instance, the encoder 320 receives information [e.g., target code rate 408] from the MAC requiring a coding rate, R, say of
2
3
. The PPDU encoder 320 is to theoretically construct a code block in a manner such that
2
3
of the final code block is payload data 502 and the remaining
1
3
are parity bits 504 used in the coding process”).
Regarding claim 7, the combination of Hedberg in view of Montorsi teaches the apparatus of claim 1, wherein the one or more processors are further configured to: identify, based at least on the target code rate, one or more LDPC codes to achieve the target code rate, wherein each of the one or more LDPC codes has a base code rate different from the base code rate of the LDPC code, for a base size of information bits different from the base size of information bits of the LDPC code (Montorsi, Figs. 5A-5D teaches multiple LDPC codes with different base code rates).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hedberg to incorporate the teachings of Montorsi by including the functionality of identifying, based on the target code rate, LDPC codes, where each LDPC code has different base code rates and different base size of information bits.
The suggestion/motivation for doing so would be a predictable and obvious design choice.
Claim 8 is a method with limitations similar to the apparatus of claim 1, and is rejected under the same rationale.
Claim 9 is a method with limitations similar to the apparatus of claim 2, and is rejected under the same rationale.
Claim 10 is a method with limitations similar to the apparatus of claim 3, and is rejected under the same rationale.
Claim 11 is a method with limitations similar to the apparatus of claim 4, and is rejected under the same rationale.
Claim 12 is a method with limitations similar to the apparatus of claim 5, and is rejected under the same rationale.
Claim 13 is a method with limitations similar to the apparatus of claim 6, and is rejected under the same rationale.
Claim 14 is a method with limitations similar to the apparatus of claim 7, and is rejected under the same rationale.
Regarding claim 15, Hedberg teaches an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to:
select, based at least on a target code rate that is different from the base code rate, a first size of information bits that is less than the base size of information bits (Hedberg, Fig. 9; para. [004], lines 1-12, “the PPDU encoder 320 can select any available code rate that is lower than or equal to the target code rate 408, since the coding system 300 enables transmission of data at a lower code rate in the same amount of time as the target code rate. Thus, the PPDU encoder 320 is configured to adapt the code rate to produce a new base code rate and structure that is defined in terms of the codewords across all the OFDM symbols that are optimized for performance with a minimum number of wasted bits. The PPDU encoder 320 packs the codewords into the transmission frame and decides what rate to use and how many bits to use per code block”); generate a second set of information bits to include a first set of information bits corresponding to the first size of information bits and one or more bits to increase a size of the second set of information to correspond to the base size of information bits (Hedberg, Fig. 5E & 5F, bit region 509; para. [0057], lines 1-6, “With continued reference to FIGS. SE and SF, note bit region 509, which is referred to as a zero padding or fill bit region. PSDU s are generally encoded with zero pad bits or fill bits added as needed so that an integral number of code blocks and an integral number of OFDM symbols can be transmitted”; para. [0058], lines 1-3, “The zero padding region 509 can be filled with zero or useless bits in some embodiments, or replicated bits in some embodiments”); encode, using the base code rate, the second set of information bits (Hedberg, para. [0039], lines 15-20, “When a packet is to be transmitted, the MAC decides the modulation mode [e.g., modulation 406] and which of these basic rates to target [e.g., target code rate 408] in the transmission. The target code rate 408 is viewed as an upper bound for the actual rate used after PPDU encoding the data into a packet”; para. [0040], lines 8-12, “In conjunction with selecting a base code rate 418, the PPDU encoder 320 selects a base code block size (e.g., 648). That is, the PPDU encoder 320 preferably determines the optimal combination of longest block size and lowest rate”) to generate parity data; and generate a codeword by concatenating the first set of information bits and the parity data to achieve the target code rate (Hedberg, para. [0044], lines 11-16, “For instance, the encoder 320 receives information [e.g., target code rate 408] from the MAC requiring a coding rate, R, say of
2
3
. The PPDU encoder 320 is to theoretically construct a code block in a manner such that
2
3
of the final code block is payload data 502 and the remaining
1
3
are parity bits 504 used in the coding process”), wherein the transmitter is configured to transmit the codeword (Hedberg, Fig. 3 teaches a transmitter device 302).
Hedberg fails to explicitly teach identify a low density parity check (LDPC) code that has a base code rate for a base size of information bits.
However, Montorsi, in an analogous art, teaches identify a low density parity check (LDPC) code that has a base code rate for a base size of information bits; (Montorsi, Figs. 5A-5D teaches partitioned LDPC parity check matrices having different LDPC code rates).
Hedberg and Montorsi are both considered to be analogous to the claimed invention because both are in the same field of LDPC error correction coding systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hedberg to incorporate the teachings of Montorsi by including the functionality of identifying LDPC codes having a base code rate for information bits.
The suggestion/motivation for doing so would be to allow for flexibility in achieving desired coding rates for transmitted data.
Claim 16 is a method with limitations similar to the apparatus of claim 2, and is rejected under the same rationale.
Claim 17 is a method with limitations similar to the apparatus of claim 3, and is rejected under the same rationale.
Claim 18 is a method with limitations similar to the apparatus of claim 4, and is rejected under the same rationale.
Claim 19 is a method with limitations similar to the apparatus of claim 6, and is rejected under the same rationale.
Claim 20 is a method with limitations similar to the apparatus of claim 7, and is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hocevar et al. (US 2007/0041458) teaches LDPC encoding including selecting codeword lengths based on payload size and available information bits, as well as shortening and puncturing operations.
Livshitz et al. (US 2009/0259915) teaches LDPC coding matrices that are expandable to support various information packet sizes and coding rates, including shortening and puncturing techniques.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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