Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US 10,680,652), hereinafter Ahn, in view of Montorsi et al. (US 11,671,115), hereinafter Montorsi.
Regarding claim 1, Ahn teaches an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a target code rate and a low density parity check (LDPC) code that has a base code rate (Ahn, Abstract, Fig. 4, rate matching unit 440) for a base size of information bits; select, based at least on the target data rate and the base code rate, a first size of information bits that is less than the base size of information bits (Ahn, Fig. 10 teaches segmentation and sizing of information bits [k] prior to LDPC encoding); generate a second set of information bits to include a first set of information bits corresponding to the first size of information bits and one or more bits to increase a size of the second set of information to correspond to the base size of information bits (Ahn, col. 12, lines 13-15, “the transmitting apparatus 400 may determine parameters [e.g., input bit length, modulation and code rate (ModCod), parameter for zero padding (or shortening)…”); and generate a codeword by concatenating the first set of information bits and the parity data to achieve the target code rate (Ahn, Fig. 1 shows codewords formed from information bits and parity bits), wherein the transmitter is configured to transmit the codeword (Ahn, Fig. 4 teaches a transmitting apparatus 400 that outputs LDPC-encoded codewords to a modulator 450 for transmission).
Ahn fails to teach encode, using the base code rate, the second set of information bits to generate parity data.
However, Montorsi, in an analogous art, teaches encode, using the base code rate, the second set of information bits to generate parity data (Montorsi, Fig. 3 & Fig. 5A-5D).
Ahn and Montorsi are both considered to be analogous to the claimed invention because both are in the same field of LDPC encoding in communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Ahn to incorporate the teachings of Montorsi by including the functionality of encoding, using a base code rate, a second set of information bits to generate parity data.
The suggestion/motivation for doing so would be that both references are directed to LDPC encoding in communication systems and the combination involves the predictable use of known LDPC techniques.
Regarding claim 2, the combination of Ahn in view of Montorsi teaches the apparatus of claim 1, wherein the target code rate is smaller than the base code rate (Ahn, Fig. 4 teaches a rate matching unit 440 that includes a puncturing, repetition, and zero elimination unit; these operations reduce the number of transmitted bits relative to the base LDPC code, which results in a target code rate that is often smaller than the base code rate).
Regarding claim 3, the combination of Ahn in view of Montorsi teaches the apparatus of claim 1, wherein in generating the second set of information bits, the one or more processors are configured to: determine, based at least on the target data rate and the base code rate, a second size of the one or more bits; and generate the one or more bits corresponding to the second size of the one or more bits (Ahn, Fig. 4 teaches a rate matching unit 440 and zero padding unit 420 which inherently requires determining how many bits must be added, removed, or padded; Fig. 10 also teaches segmentation of transport blocks based on Kr and Kldpc).
Regarding claim 4, the combination of Ahn in view of Montorsi teaches the apparatus of claim 1, wherein the one or more processors are further configured to: generate, based at least on the set of masked bits and the second set of information bits, a third set of information bits corresponding to the base size of information bits (Ahn, Fig. 4 teaches zero padding, rate matching, and interleaving/re-ordering; a third set of information bits is just the resulting bit set after the rate matching unit processing); encode, using the base code rate, the third set of information bits to generate second parity data (Ahn, Fig. 4 & Fig.7 teaches LDPC encoding and rate matching); and generate the codeword by concatenating the first set of information bits and the second parity data to achieve the target code rate (Ahn, Fig. 1 & Fig. 4 teaches codeword generation and transmission).
Both Ahn and Montorsi fail to explicitly teach determine, based at least on a coded bit error rate or a frame error probability, a set of masked bits corresponding to the base size of information bits, however Ahn teaches a transmitter/receiver system (Ahn, Fig. 4 & Fig. 5) that uses rate matching operations that mask or exclude bits and Montorsi teaches multi-rate LDPC codes.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Ahn to incorporate the teachings of Montorsi by including the functionality of determining a set of bits to be masked or excluded based on coded bit error rate or frame error probability when performing LDPC encoding and rate matching.
The suggestion/motivation for doing so would be that BER/FER-based selection is a predictable and routine technique in communication systems, used to guide coding decisions.
Regarding claim 5, the combination of Ahn in view of Montorsi teaches the apparatus of claim 1, wherein the second set of information bits are encoded using the identified LDPC code to generate the parity data (Ahn, Fig.1 teaches a codeword formed from information bits and parity bits; Fig. 4 teaches an LDPC encoder 430; Fig. 7 teaches an LDPC encoder receiving information bits and outputting parity bits).
Regarding claim 6, the combination of Ahn in view of Montorsi teaches the apparatus of claim 1, wherein a ratio of the first size of information bits to a size of the codeword is equal to the target code rate (Ahn, Figs. 1, 4 & 10 teach LDPC encoding in which a codeword is generated from a defined number of information bits and parity bits, where the code rate is determined by the ration of number of information bits to the total codeword length).
Regarding claim 7, the combination of Ahn in view of Montorsi teaches the apparatus of claim 1, wherein the one or more processors are further configured to: identify, based at least on the target code rate, one or more LDPC codes to achieve the target code rate, wherein each of the one or more LDPC codes has a base code rate different from the base code rate of the LDPC code, for a base size of information bits different from the base size of information bits of the LDPC code (Montorsi, Figs. 5A-5D teaches multiple LDPC codes with different base code rates).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Ahn to incorporate the teachings of Montorsi by including the functionality of identifying, based on the target code rate, LDPC codes, where each LDPC code has different base code rates and different base size of information bits.
The suggestion/motivation for doing so would be a predictable and obvious design choice.
Claim 8 is a method with limitations similar to the apparatus of claim 1, and is rejected under the same rationale.
Claim 9 is a method with limitations similar to the apparatus of claim 2, and is rejected under the same rationale.
Claim 10 is a method with limitations similar to the apparatus of claim 3, and is rejected under the same rationale.
Claim 11 is a method with limitations similar to the apparatus of claim 4, and is rejected under the same rationale.
Claim 12 is a method with limitations similar to the apparatus of claim 5, and is rejected under the same rationale.
Claim 13 is a method with limitations similar to the apparatus of claim 6, and is rejected under the same rationale.
Claim 14 is a method with limitations similar to the apparatus of claim 7, and is rejected under the same rationale.
Regarding claim 15, the claim teaches similar limitations to claim 1, differing primarily in identifying singly an LDPC code having a base code rate for a base size of information bits. As discussed above in claim 1’s rejection, the cited references teach the limitations of claim 15. Ahn teaches an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a low density parity check (LDPC) code that has a base code rate (Ahn, Abstract & Fig. 4, rate matching unit 440) for a base size of information bits; select, based at least on the base code rate, a target code rate and a first size of information bits that is less than the base size of information bits (Ahn, Fig. 10 teaches segmentation and sizing of information bits [k] prior to LDPC encoding); generate a second set of information to include a first set of information bits corresponding to the first size of information bits and one or more bits to increase a size of the second set of information to correspond to the base size of information bits (Ahn, col. 12, lines 13-15, “the transmitting apparatus 400 may determine parameters [e.g., input bit length, modulation and code rate (ModCod), parameter for zero padding (or shortening)…”); and generate a codeword by concatenating the first set of information bits and the parity data to achieve the target code rate (Ahn, Fig. 1 shows codewords formed from information bits and parity bits), wherein the transmitter is configured to transmit the codeword (Ahn, Fig. 4 teaches a transmitting apparatus 400 that outputs LDPC-encoded codewords to a modulator 450 for transmission).
Ahn fails to teach encode, using the base code rate, the second set of information bits to generate parity data.
However, Montorsi, in an analogous art, teaches encode, using the base code rate, the second set of information bits to generate parity data (Montorsi, Fig. 3 & Fig. 5A-5D).
Ahn and Montorsi are both considered to be analogous to the claimed invention because both are in the same field of LDPC encoding in communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Ahn to incorporate the teachings of Montorsi by including the functionality of encoding, using a base code rate, a second set of information bits to generate parity data.
The suggestion/motivation for doing so would be that both references are directed to LDPC encoding in communication systems and the combination involves the predictable use of known LDPC techniques.
Claim 16 is a method with limitations similar to the apparatus of claim 2, and is rejected under the same rationale.
Claim 17 is a method with limitations similar to the apparatus of claim 3, and is rejected under the same rationale.
Claim 18 is a method with limitations similar to the apparatus of claim 4, and is rejected under the same rationale.
Claim 19 is a method with limitations similar to the apparatus of claim 6, and is rejected under the same rationale.
Claim 20 is a method with limitations similar to the apparatus of claim 7, and is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Andersson et al. (US 2021/0266017) teaches LDPC encoding and rate matching techniques for achieving target code rates from base LDPC codes.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112