DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 15, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 11, 15, and 20 there is no discussion of a SRAM structure or what is to be included or exclude as read write circuity:
Paragraph 49 states:
Moreover, in one example implementation illustrated in FIG. 8, an array 151 of the CFETs 100 may be incorporated in a memory device. For example, the array 151 may be coupled with read/write circuitry 152 to define a static random-access memory (SRAM) 150. The array 151 may similarly be used in other memory devices as well, as will be appreciated by those skilled in the art.
However, it is unclear what form of SRAM is being used it could be a 4T 6T 8T or potentially a 1T if it 4T-8T.
Applicant is not claim interconnecting the CFET to form a SRAM and providing read/write
Further applicant merely set forth a desired function and has not adequately defined the required circuitry need to accomplish the outcome. See mpep 2173.05g
Thus, one could not determine what is sufficient read/write circuitry coupled to the plurality of CFETs to define a static random-access memory (SRAM).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10, 12-14 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen 20230066265 (cited on ids) in view of Hong 20220231134 and Mears 20220476047 (cited on ids).
As to claim 1-4, Chen teaches A method for making a semiconductor device comprising: forming a plurality of complimentary field effect transistors (CFETs) each CFET comprising an n-channel field effect transistor (NFET) ( figure 1b items 102a1 item 22 paragraph 27) and a p-channel field effect transistor (PFET) ( figure 1b items 102a2 item 24 paragraph 27) stacked in vertical relation (figure 1b), each of the NFET and PFET comprising spaced apart source and drain regions defining respective nanostructured channels therebetween (source drains items 109 with channels 122 and source drains item 11 with source drains 124 as the channels); a gate overlying both of the channels (items 112 paragraph 23); and at least one isolation layer between the NFET and the PFET (item 126). Chen teaches the isolation between the sources and the drains of the NFET and the PFET (figure 1b)
Chen does not teach a diffusion barrier comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Mear teaches a diffusion barrier comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (abstract).
Hong teach provide paragraph 4 the use of diffusion breaks between devices:
Diffusion breaks in semiconductor devices generally bring two distinct functionalities to a semiconductor device. First, they provide enhanced electrical isolation for adjacent transistor devices, and second, they provide a barrier against the diffusion of dopants or contaminants from one transistor to another. Diffusion breaks generally are comprised of a bulk dielectric material that fills a gap formed between transistors. This gap may be narrow, such as approximately the width of the gate (E.G, a single diffusion break, (SDB)), or wide such as the distance between adjacent features (E.G, double diffusion breaks), or more. Such diffusion breaks generally stretch, vertically, from a trench in the semiconductor substrate, all the way to the top of the transistor level.
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to include a diffusion barrier structure of Mears including: a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, in the isolation of Chen.
To improve diffusion barrier between the source and drain improving diffusion prevention as suggested by Mears (paragraph 41).
As to claim 5, Chen is silent in regards to the type of nanostructure used.
Mears teaches nanostructured layers for channels maybe nanowires (paragraph 60)
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the nanostructure channels as nanowires to use convention and known nanostructured channels to provide predictable outcomes of Gate all around channels.
As to claim 6, Mears teaches silicon for the semiconductor (paragraph 45).
As to claims 7 and 8, Mears teaches oxygen and carbon (paragraph 45).
As to claim 10, Mears teach wherein forming the at least one non-semiconductor monolayer comprises forming alternating layers of oxygen and carbon monolayers specifically a monolayer per abstract.
As to claim 12, Chen teaches A method for making a semiconductor device comprising: forming a plurality of complimentary field effect transistors (CFETs) each CFET comprising an n-channel field effect transistor (NFET) ( figure 1b items 102a1 item 22 paragraph 27) and a p-channel field effect transistor (PFET) ( figure 1b items 102a2 item 24 paragraph 27) stacked in vertical relation (figure 1b), each of the NFET and PFET comprising spaced apart source and drain regions defining respective nanostructured channels therebetween (source drains items 109 with channels 122 and source drains item 11 with source drains 124 as the channels); a gate overlying both of the channels (items 112 paragraph 23); and at least one isolation layer between the NFET and the PFET (item 126). Chen teaches the isolation between the sources and the drains of the NFET and the PFET (figure 1b)
Chen does not teach a diffusion barrier comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Mear teaches a diffusion barrier comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (abstract).
Hong teach provide paragraph 4 the use of diffusion breaks between devices:
Diffusion breaks in semiconductor devices generally bring two distinct functionalities to a semiconductor device. First, they provide enhanced electrical isolation for adjacent transistor devices, and second, they provide a barrier against the diffusion of dopants or contaminants from one transistor to another. Diffusion breaks generally are comprised of a bulk dielectric material that fills a gap formed between transistors. This gap may be narrow, such as approximately the width of the gate (E.G, a single diffusion break, (SDB)), or wide such as the distance between adjacent features (E.G, double diffusion breaks), or more. Such diffusion breaks generally stretch, vertically, from a trench in the semiconductor substrate, all the way to the top of the transistor level.
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to include a diffusion barrier structure of Mears including: a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, in the isolation of Chen.
To improve diffusion barrier between the source and drain improving diffusion prevention as suggested by Mears (paragraph 41).
Chen is silent in regards to the type of nanostructure used.
Mears teaches nanostructured layers for channels maybe nanowires (paragraph 60)
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the nanostructure channels as nanowires to use convention and known nanostructured channels to provide predictable outcomes of Gate all around channels.
As to claim 13, Mears teaches silicon for the semiconductor (paragraph 45).
As to claim 14, Mears teaches wherein the at least one non-semiconductor monolayer comprises at least one of oxygen and carbon (paragraph 45).
As to claims 16 and 17 , Chen teaches A method for making a semiconductor device comprising: forming a plurality of complimentary field effect transistors (CFETs) each CFET comprising an n-channel field effect transistor (NFET) ( figure 1b items 102a1 item 22 paragraph 27) and a p-channel field effect transistor (PFET) ( figure 1b items 102a2 item 24 paragraph 27) stacked in vertical relation (figure 1b), each of the NFET and PFET comprising spaced apart source and drain regions defining respective nanostructured channels therebetween (source drains items 109 with channels 122 and source drains item 11 with source drains 124 as the channels); a gate overlying both of the channels (items 112 paragraph 23); and at least one isolation layer between the NFET and the PFET (item 126). Chen teaches the isolation between the sources and the drains of the NFET and the PFET (figure 1b)
Chen does not teach a diffusion barrier comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Mear teaches a diffusion barrier comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, silicon (paragraph 45), and at least one non-semiconductor monolayer, comprising at least one of carbon and oxygen (paragraph 45), constrained within a crystal lattice of adjacent base semiconductor portions (abstract).
Hong teach provide paragraph 4 the use of diffusion breaks between devices:
Diffusion breaks in semiconductor devices generally bring two distinct functionalities to a semiconductor device. First, they provide enhanced electrical isolation for adjacent transistor devices, and second, they provide a barrier against the diffusion of dopants or contaminants from one transistor to another. Diffusion breaks generally are comprised of a bulk dielectric material that fills a gap formed between transistors. This gap may be narrow, such as approximately the width of the gate (E.G, a single diffusion break, (SDB)), or wide such as the distance between adjacent features (E.G, double diffusion breaks), or more. Such diffusion breaks generally stretch, vertically, from a trench in the semiconductor substrate, all the way to the top of the transistor level.
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to include a diffusion barrier structure of Mears including: a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, in the isolation of Chen.
To improve diffusion barrier between the source and drain improving diffusion prevention as suggested by Mears (paragraph 41).
As to claim 18, Chen is silent in regards to the type of nanostructure used.
Mears teaches nanostructured layers for channels maybe nanowires (paragraph 60)
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the nanostructure channels as nanowires to use convention and known nanostructured channels to provide predictable outcomes of Gate all around channels.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen 20230066265 (cited on ids) in view of Hong 20220231134 and Mears 20220476047 in view of Weeks 20220005926.
As to claims 9 and 19, Mears does not teach wherein forming the at least one non-semiconductor monolayer comprises forming alternating layers of oxygen and carbon monolayers.
Weeks teaches forming the at least one non-semiconductor monolayer comprises forming alternating layers of oxygen and carbon monolayers (figure 5 paragraph 22 and 60-61).
Weeks also suggest such structures act as diffusion barriers paragraph 41.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the at least one non-semiconductor monolayer comprises forming alternating layers of oxygen and carbon monolayers as suggested by Weeks.
To use conventional superlattice structures to provide expected outcomes of a diffusion barrier as suggested by Weeks.
Claim(s) 11, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable Chen 20230066265 in view of Hong 20220231134 and Mears 20220476047 in view Chanemougame 20220102362.
As to claims 11, 15 and 20 Chen does not teach providing wiring to configure the CFETs and providing read write circuitry.
Chanemougame teach integration of CFET into a SRAM figure 2 and 4-6.
Thus, it would have been obvious to one ordinary art at the time of filing to integrate the CFETs of Chen SRAM cells and to provide read write circuitry to access the SRAM cells.
One would have been so motivated to use the CFET in conventional technologies providing expected outcomes of reduced noise due to the isolation and improved diffusion properties.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of copending Application No. 18790345 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because
While 187907345
Claim 1 recites: plurality of complimentary field effect transistors (CFETs), each CFET comprising an n-channel field effect transistor (NFET) and a p-channel field effect transistor (PFET) stacked in vertical relation, each of the NFET and PFET comprising spaced apart source and drain regions defining respective channels therebetween; a gate overlying both of the channels; and at least one isolation layer between the NFET and the PFET and comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Claim 12: a plurality of complimentary field effect transistors (CFETs), each CFET comprising an n-channel field effect transistor (NFET) and a p-channel field effect transistor (PFET) stacked in vertical relation, each of the NFET and PFET comprising spaced apart source and drain regions defining respective channels therebetween, and each of the channels comprising a plurality of nanowires; a gate overlying both of the channels; a source isolation layer between the source regions of the NFET and PFET; and a drain isolation layer between the drain regions of the NFET and PFET; the source isolation layer and the drain isolation layer each comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Claim 16 recites: a plurality of complimentary field effect transistors (CFETs), each CFET comprising an n-channel field effect transistor (NFET) and a p-channel field effect transistor (PFET) stacked in vertical relation, each of the NFET and PFET comprising spaced apart source and drain regions defining respective channels therebetween; a gate overlying both of the channels; and at least one isolation layer between the NFET and the PFET and comprising a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions and comprising at least one of carbon and oxygen.
To have the device one would need to form such a device.
Claim 2 corresponds to claim 2
Claim 3 corresponds to claim 3.
Claim 4 corresponds to claim 4.
Claim 5 corresponds to claim 5.
Claim 6 corresponds to claim 6.
Claim 8 corresponds to claim 8.
Claim 9 corresponds to claim 9.
Claim 10 corresponds to claim 10.
Claim 11 corresponds to claim 11.
Claim 13 corresponds to claim 13.
Claim 14 corresponds to claim 14.
Claim 15 corresponds to claim 15.
Claim 17 corresponds to claim 17.
Claim 18 corresponds to claim 18.
Claim 19 corresponds to claim 19.
Claim 20 corresponds to claim 20.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gardner 20220238652 teaches diffusion breaks items 106 in a vertical stack of transistors figure 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
