DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamada (US 2017/0093402).
Claim 1, Yamada discloses a dual rail circuit (Fig. 10) comprising:
a first circuit (inverter 21) in a first power domain (Vext), the first circuit
comprising an input port (IN) and an output port (LS); and
a second circuit (latch circuit 24) in a second power domain (Vint) different from
the first power domain (see P[0053]. Vext>Vint>1/Vext...), the second circuit (latch circuit 24) coupled to the input port (IN) of the first circuit and the output port (LS) of the
first circuit, wherein the second circuit is configured to store a signal received from the first circuit and provide an output signal based on the stored signal when the first power domain loses power (see P[0113]… the latch circuit 24 maintains the signal levels of the output signals OUTA and OUTB of before the external power supply voltage Vext drops and then continues to output them as the interface output signal. Therefore, the circuit malfunction caused by the voltage fluctuation can be prevented…; and see P[0072]… In case that the external power supply is shutdown or halted by a power failure or the like during the device operation…).
Claim 2, Yamada discloses the circuit of claim 1, wherein the second circuit
comprising cross-coupled logic gates (NOR gate NR1 and NOR gate NR2 are cross-
coupled).
Claim 3, Yamada discloses the circuit of claim 2, wherein the cross-coupled logic
gates include a first NOR gate (NOR gate NR1, see P[0096]) and a second NOR gate
(NOR gate, see P[0095]) cross-coupled with the first NOR gate.
Claim 4, Yamada discloses the circuit of claim 3, wherein an input port (IN) of the
first circuit is coupled to the first NOR gate (NOR gate NR1) and an output port (LS) of
the first circuit is coupled to the second NOR gate (NOR gate NR2).
Claim 5, Yamada discloses the circuit of claim 3, wherein an output port (OUTB)
of the first NOR gate is coupled to an input port (gates of transistors MP7 and MN7) of
the second NOR gate (NOR gate NR2).
Claim 6, Yamada discloses the circuit of claim 3, wherein an output port (OUTA)
of the second NOR gate is coupled to an input port (gates of NR1) of the first NOR gate.
Claim 7, Yamada discloses the circuit of claim 1, wherein the first circuit
comprises a voltage supply port (Vext).
Claim 8, Yamada discloses the circuit of claim 4, wherein the voltage supply port
(Vext) is coupled to the input port (IN is coupled to Vext through MP1).
Claim 9, Yamada discloses the circuit of claim 1, wherein the first circuit
comprises an inverter (Inverter 21).
Claim 10, Yamada discloses the circuit of claim 1, wherein the first power domain
is higher than the second power domain (see P[0053]. Vext>Vint>1/Vext...).
Claim 11, Yamada discloses the circuit of claim 3, wherein the first NOR gate
includes a VDD port (Vint).
Claim 12, Yamada discloses the circuit of claim 3, wherein the second NOR gate
includes a VDD port (Vint).
Claim 13, Yamada discloses a dual rail circuit (Fig. 10) comprising:
a first circuit (inverter 21) in a first power domain (Vext), the first circuit
comprising an input port (IN) and an output port (LS); and
a second circuit (Latch circuit 24) in a second power domain (Vint) different from
the first power domain (see P[0053]. Vext>Vint>1/Vext...), the second circuit coupled
to the input port of the first circuit (IN) and the output port of the first circuit (LS), the
second circuit comprising cross-coupled logic gates (NOR gate NR1 and NOR gate
NR2 are cross-coupled), wherein the second circuit is configured to store a signal received from the first circuit and provide an output signal based on the stored signal when the first power domain loses power (see P[0113]… the latch circuit 24 maintains the signal levels of the output signals OUTA and OUTB of before the external power supply voltage Vext drops and then continues to output them as the interface output signal. Therefore, the circuit malfunction caused by the voltage fluctuation can be prevented…; and see P[0072]… In case that the external power supply is shutdown or halted by a power failure or the like during the device operation…).
Claim 14, Yamada discloses the circuit of claim 13, wherein the second circuit comprising cross-coupled logic gates (NOR gate NR1 and NOR gate NR2 are cross- coupled).
Claim 15, Yamada discloses the circuit of claim 13, wherein the cross-coupled logic gates include a first NOR gate (NOR gate NR1) and a second NOR gate (NOR gate NR2) cross-coupled with the first NOR gate.
Claim 16, Yamada discloses the circuit of claim 13, wherein an input port of the first circuit is coupled to the first NOR gate and an output port of the first circuit is coupled to the second NOR gate.
Claim 17, Yamada discloses the circuit of claim 13, wherein an output port (OUTB) of the first NOR gate (NOR gate NR1) is coupled to an input port (gates transistors MP7 and MN7) of the second NOR gate (NOR gate NR2).
Claim 18, Yamada discloses a method (Fig. 10) comprising:
receiving, by a second circuit (Latch circuit 24), a first signal (LS) from a first circuit (Inverter 21) receiving a first supply signal (Vext) associated with a first power domain (Vext); receiving, by the second circuit, a second supply signal (Vint) and a ground signal (Vss) associated with a second power domain (Vint), wherein the second circuit is configured to store a signal received from the first circuit and provide an output signal based on the stored signal when the first power domain loses power (see P[0113]… the latch circuit 24 maintains the signal levels of the output signals OUTA and OUTB of before the external power supply voltage Vext drops and then continues to output them as the interface output signal. Therefore, the circuit malfunction caused by the voltage fluctuation can be prevented…; and see P[0072]… In case that the external power supply is shutdown or halted by a power failure or the like during the device operation…); receiving, by the second circuit, a floating signal from the first circuit after the first circuit no longer receives the first supply signal (Fig. 10 of Yamada is identical structure to applicant's Fig. 2, according MPEP 2112.01, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent); and providing, by the second circuit, a second
signal (OUTA), wherein the second signal is coupled to one of the second supply signal (Vint) or the ground signal (Vss).
Claim 19, Yamada discloses the method of claim 18, further comprising storing
the first signal in the second circuit (Latch circuit 24 is a storing circuit).
Claim 20, Yamada discloses the method of claim 19, further comprising providing
the second signal based on the first signal (OUTA is based on signal LS).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/ANH Q TRAN/Primary Examiner, Art Unit 2844 3/19/26