DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on October 16, 2024 has been fully considered by the examiner.
Specification
3. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it recites “are provided” in line 2, which can be inferred, and lines 1-2 repeat information given in the title.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-9, 11, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, et al (US 20230337418 A1), hereinafter Lee.
Regarding independent claim 1, Lee teaches a memory device (FIG. 14, 400) comprising:
a first semiconductor structure (FIG. 14, e.g., Memory Cell Array (MCA) 480a; ¶ [0032]) comprising a first memory block (e.g., the Sub-Cell Array (SCA) in FIG. 1 corresponding to Sub-Peripheral Circuit SPC22 in FIG. 3; ¶ [0032-0034]); and
a second semiconductor structure (FIG. 14, e.g., Core Control Circuit (CCC) 485a; ¶ [0032]) comprising a driver circuit (the CCC of FIG. 1 comprises an array of SPCs, which are shown in FIG. 2 to include a wordline driver region RWD, which includes sub-wordline drivers; ¶ [0040]),
wherein the first semiconductor structure and the second semiconductor structure are stacked along a first direction (FIG. 1, CCC and MCA are stacked in the Z direction; ¶ [0032]), and
wherein the driver circuit at least partially overlaps with the first memory block in a plan view (FIG. 1, each SCA overlaps a corresponding SPC; ¶ [0032-0033]) perpendicular to the first direction (FIG. 1, SCAs overlap SPCs “horizontally” in an XY plane perpendicular to the Z-direction stacking).
Regarding independent claim 15, Lee teaches a method of forming a memory device (¶ [0093-0151]), comprising:
forming a first semiconductor structure (FIG. 14, e.g., Memory Cell Array (MCA) 480a; ¶ [0032]) based on forming a first memory block (e.g., the Sub-Cell Array (SCA) in FIG. 1 corresponding to Sub-Peripheral Circuit SPC22 in FIG. 3; ¶ [0032-0034]);
forming a second semiconductor structure (FIG. 14, e.g., Core Control Circuit (CCC) 485a; ¶ [0032]) based on forming a driver circuit (the CCC of FIG. 1 comprises an array of SPCs, which are shown in FIG. 2 to include a wordline driver region RWD, which includes sub-wordline drivers; ¶ [0040]); and
stacking the first semiconductor structure and the second semiconductor structure along a first direction (FIG. 1, CCC and MCA are stacked in the Z direction; ¶ [0032]), wherein the driver circuit at least partially overlaps with the first memory block in a plan view (FIG. 1, each SCA overlaps a corresponding SPC; ¶ [0032-0033]) perpendicular to the first direction (FIG. 1, SCAs overlap SPCs “horizontally” in an XY plane perpendicular to the Z-direction stacking).
Regarding independent claim 20, Lee teaches a memory system (FIG. 27, 1200), comprising:
a memory device (FIG. 27, 1230; FIG. 14, 400; ¶ [0187-0188]) comprising:
a first semiconductor structure (FIG. 14, e.g., Memory Cell Array (MCA) 480a; ¶ [0032]) comprising a first memory block (e.g., the Sub-Cell Array (SCA) in FIG. 1 corresponding to Sub-Peripheral Circuit SPC22 in FIG. 3; ¶ [0032-0034]); and
a second semiconductor structure (FIG. 14, e.g., Core Control Circuit (CCC) 485a; ¶ [0032]) comprising a driver circuit (the CCC of FIG. 1 comprises an array of SPCs, which are shown in FIG. 2 to include a wordline driver region RWD, which includes sub-wordline drivers; ¶ [0040]),
wherein the first semiconductor structure and the second semiconductor structure are stacked along a first direction (FIG. 1, CCC and MCA are stacked in the Z direction; ¶ [0032]), and
wherein the driver circuit at least partially overlaps with the first memory block in a plan view (FIG. 1, each SCA overlaps a corresponding SPC; ¶ [0032-0033]) perpendicular to the first direction (FIG. 1, SCAs overlap SPCs “horizontally” in an XY plane perpendicular to the Z-direction stacking); and
a controller coupled to the memory device and configured to control the memory device (FIG. 27, AP 1210; ¶ [0187]).
Regarding claim 2, Lee teaches the limitations of claim 1.
Lee further teaches the first semiconductor structure further comprises a second memory block and a third memory block (e.g., the SCAs in FIG. 1 corresponding to SPC21 and SPC23, respectively, in FIG. 3),
wherein word lines coupled to memory cells of the first memory block are arranged in order (FIG. 18, a representative SCA includes word lines in order from WL0..WL7), and
wherein an even-numbered word line is coupled to memory cells of the second memory block (FIG. 18, a representative SCA includes even-numbered word lines WL0, WL2, WL4, and WL6 coupled to memory cells MC), and an odd-numbered word line is coupled to memory cells of the third memory block (FIG. 18, representative SCA includes odd-numbered word lines WL1, WL3, WL5, and WL7 coupled to memory cells MC).
Regarding claim 3, Lee teaches the limitations of claim 2.
Lee further teaches the first memory block is positioned between the second memory block and the third memory block along a second direction perpendicular to the first direction (FIGS. 1 and 3, the “first memory block” (SCA corresponding to SPC22) is positioned between the “second memory block” (SCA corresponding to SPC21) and “third memory block” (SCA corresponding to SPC23) along the X direction, which is perpendicular to the Z direction).
Regarding claim 4, Lee teaches the limitations of claim 3.
Lee further teaches the second memory block is positioned adjacent to the first memory block on a first side of the first memory block, and the third memory block is positioned adjacent to the first memory block on a second side of the first memory block (FIGS. 1 and 3, the “second memory block” (SCA corresponding to SPC21) and “third memory block” (SCA corresponding to SPC23) are positioned adjacent to and on different sides of the “first memory block” (SCA corresponding to SPC22)).
Regarding claim 5, Lee teaches the limitations of claim 2.
Lee further teaches the driver circuit comprises a first set of word line drivers and a second set of word line drivers,
wherein the even-numbered word line is coupled to a corresponding word line driver of the first set of word line drivers, and
wherein the odd-numbered word line is coupled to a corresponding word line driver of the second set of word line drivers (FIG. 18 illustrates two “sets” of sub-wordline drivers SWD, of which one set drives odd word lines from the left side and another set drives even word lines from the right side).
Regarding claim 6, Lee teaches the limitations of claim 3.
Lee further teaches the second semiconductor structure further comprises a sensing circuit (FIG. 2, RSA; ¶ [0039] teaches “each sub peripheral circuit SPC may include a sense amplifier region RSA”), and
the sensing circuit at least partially overlaps with the first memory block in the plan view (¶ [0005] teaches “each sub peripheral circuit is disposed under each sub cell array”; FIGS. 2-7 and ¶ [0039] teach “each sub peripheral circuit SPC may include a sense amplifier region RSA”; therefore, the sensing circuit at least partially overlaps with the first memory block).
Regarding claim 7, Lee teaches the limitations of claim 6.
Lee further teaches the sensing circuit comprises a first set of sense amplifiers and a second set of sense amplifiers (FIG. 6, e.g., SPC21 includes a “set” of “even” sense amplifiers SA6-SA12 and a “set” of “odd” sense amplifiers SA5-SA11),
wherein bit lines coupled to memory strings of the first memory block are arranged in order (in FIG. 18, a representative memory block shows bit lines arranged in order BT0, BT1, BT2, etc.),
wherein an even-numbered bit line is coupled to a corresponding sense amplifier of the first set of sense amplifiers (FIG. 6, e.g., BL6 is coupled to SA6 of the “even” set), and
wherein an odd-numbered bit line is coupled to a corresponding sense amplifier of the second set of sense amplifiers (FIG. 6, BL5 is coupled to SA5 of the “odd” set).
Regarding claim 8, Lee teaches the limitations of claim 7.
Lee further teaches the first semiconductor structure further comprises a fourth memory block and a fifth memory block (FIGS. 1 and 3, e.g., “fourth memory block” may be the SCA corresponding to SPC12 and “fifth memory block” may be the SCA corresponding to SPC32),
wherein a first bit line coupled to a first memory string of the fourth memory block is coupled to a corresponding sense amplifier of the first set of sense amplifiers (FIG. 6, in a representative SPC (SPC21), a “first bit line” may be BL6 coupled to the first (even) set of sense amplifiers, which may be coupled to an SCA memory string as shown in FIG. 22), and
wherein a second bit line coupled to a second memory string of the fifth memory block is coupled to a corresponding sense amplifier of the second set of sense amplifiers (FIG. 6, in a representative SPC (SPC21), a “second bit line” may be BL5 coupled to the second (odd) set of sense amplifiers, which may be coupled to a second SCA memory string as shown in FIG. 22).
Regarding claim 9, Lee teaches the limitations of claim 8.
Lee further teaches the first memory block is positioned between the fourth memory block and the fifth memory block along a third direction perpendicular to the first direction and the second direction (FIGS. 1 and 3, the “first memory block” (SCA corresponding to SPC22) is positioned between the “fourth memory block” (SCA corresponding to SPC12) and “fifth memory block” (SCA corresponding to SPC32) along the Y direction, which is perpendicular to the X and Z directions).
Regarding claim 11, Lee teaches the limitations of claim 1.
Lee further teaches the memory device comprises a DRAM memory device (¶ [0184]).
Regarding claim 16, Lee teaches the limitations of claim 15.
Lee further teaches the first semiconductor structure further comprises a second memory block and a third memory block (e.g., the SCAs in FIG. 1 corresponding to SPC21 and SPC23, respectively, in FIG. 3),
wherein word lines coupled to memory cells of the first memory block are arranged in order (FIG. 18, a representative SCA includes word lines in order from WL0..WL7), and
wherein an even-numbered word line is coupled to memory cells of the second memory block (FIG. 18, a representative SCA includes even-numbered word lines WL0, WL2, WL4, and WL6 coupled to memory cells MC), and an odd-numbered word line is coupled to memory cells of the third memory block (FIG. 18, representative SCA includes odd-numbered word lines WL1, WL3, WL5, and WL7 coupled to memory cells MC).
Regarding claim 17, Lee teaches the limitations of claim 16.
Lee further teaches the second memory block is positioned adjacent to the first memory block on a first side of the first memory block, and the third memory block is positioned adjacent to the first memory block on a second side of the first memory block (FIGS. 1 and 3, the “second memory block” (SCA corresponding to SPC21) and “third memory block” (SCA corresponding to SPC23) are positioned adjacent to and on different sides of the “first memory block” (SCA corresponding to SPC22)).
Regarding claim 18, Lee teaches the limitations of claim 16.
Lee further teaches the driver circuit comprises a first set of word line drivers and a second set of word line drivers,
wherein the even-numbered word line is coupled to a corresponding word line driver of the first set of word line drivers, and
wherein the odd-numbered word line is coupled to a corresponding word line driver of the second set of word line drivers (FIG. 18 illustrates two “sets” of sub-wordline drivers SWD, of which one set drives odd word lines from the left side and another set drives even word lines from the right side).
Regarding claim 19, Lee teaches the limitations of claim 15.
Lee further teaches the second semiconductor structure comprises a sensing circuit comprising a first set of sense amplifiers and a second set of sense amplifiers (FIG. 6, e.g., SPC21 includes a “set” of “even” sense amplifiers SA6-SA12 and a “set” of “odd” sense amplifiers SA5-SA11),
wherein the sensing circuit at least partially overlaps with the first memory block in the plan view (¶ [0005] teaches “each sub peripheral circuit is disposed under each sub cell array”; FIGS. 2-7 and ¶ [0039] teach “each sub peripheral circuit SPC may include a sense amplifier region RSA”; therefore, the sensing circuit at least partially overlaps with the first memory block),
wherein bit lines coupled to memory strings of the first memory block are arranged in order (in FIG. 18, a representative memory block shows bit lines arranged in order BT0, BT1, BT2, etc.),
wherein an even-numbered bit line is coupled to a corresponding sense amplifier of the first set of sense amplifiers (FIG. 6, e.g., BL6 is coupled to SA6 of the “even” set), and
wherein an odd-numbered bit line is coupled to a corresponding sense amplifier of the second set of sense amplifiers (FIG. 6, BL5 is coupled to SA5 of the “odd” set).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al (US 20230337418 A1), hereinafter Lee, in view of Sukekawa (US 20190363074 A1).
Regarding claim 12, Lee teaches the limitations of claim 1.
Lee does not teach the first semiconductor structure and the second semiconductor structure comprise bonding contacts that bond the first semiconductor structure and the second semiconductor structure together, wherein the bonding contacts are isolated by an isolating material.
Sukekawa teaches the first semiconductor structure and the second semiconductor structure comprise bonding contacts (FIG. 2, e.g., BE1 and BE2; ¶ [0015-0017]) that bond the first semiconductor structure (FIG. 2, memory chip 10; ¶ [0014]) and the second semiconductor structure together (FIG. 2, logic chip 20; ¶ [0014]), wherein the bonding contacts are isolated by an isolating material (FIG. 2, interlayer dielectric films 18 and 25; ¶ [0015-0016]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Sukekawa into the method of Lee to include bonding electrodes to bond the memory chip to the logic chip such that the bit lines and sub-word lines provided on the memory chip are electrically connected to the logic chip (Sukekawa ¶ [0017]). The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of allowing the memory cell array and logic circuit to be fabricated by separate processes, thereby allowing the individual process conditions to be optimized (Sukekawa ¶ [0002]).
Regarding claim 13, Lee as modified by Sukekawa teaches the limitations of claim 12.
Sukekawa further teaches the first semiconductor structure further comprises a first interconnect layer (FIG. 2, wiring layer 17; ¶ [0015]) positioned between the first memory block and the bonding contacts along the first direction (FIG. 2, interconnect layer 17 is placed between memory cell array 11 and bonding electrodes BE1 in the Z direction; ¶ [0015]).
Lee further teaches the first interconnect layer comprises metal layers (FIG. 16 shows wiring pattern 240 and conductive layer 120 as a conductive material such as aluminum, copper, etc. (¶ [0096]))
Sukekawa further teaches wherein a word line in the first memory block is connected to a respective one of the bonding contacts through at least one of the metal layers (¶ [0015] teaches “word line connection region 13 is connected to the overlaying wiring layer 17” and “wiring layer 17 are connected to a plurality of bonding electrodes BE1”).
Regarding claim 14, Lee as modified by Sukekawa teaches the limitations of claim 13.
Sukekawa further teaches a bit line in the first memory block is connected to a respective one of the bonding contacts through at least two of the metal layers (¶ [0015] teaches “bit line connection region 12 is connected to an overlaying wiring layer 17 via conductor 15” and “Wirings on the wiring layer 17 are connected to a plurality of bonding electrodes BE1.” Therefore, bit lines pass through at least wiring layers 15 and 17 between the first memory block and the bonding contacts.)
11. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al (US 20230337418 A1), hereinafter Lee, in view of Scheuerlein (US 20030202404 A1).
Regarding claim 10, Lee teaches the limitations of claim 7.
Lee does not teach the second semiconductor structure further comprises a first column decoder coupled to the first set of sense amplifiers, and a second column decoder coupled to the second set of sense amplifiers,
wherein the first column decoder and the second column decoder overlap with the first memory block in the plan view.
Scheuerlein teaches the second semiconductor structure further comprises a first column decoder (FIG. 1, column decoder C above the dashed line of memory array 4) coupled to the first set of sense amplifiers (FIG. 4, 460), and a second column decoder (FIG. 1, column decoder C below dashed line of memory array 4) coupled to the second set of sense amplifiers (FIG. 4, SA immediately below the dashed line of memory array 4),
wherein the first column decoder and the second column decoder overlap with the first memory block in the plan view (FIG. 1, both column decoders for memory array 4 are underneath its associated memory array; ¶ [0006] teaches “each of the row decoder and column decoder circuits is associated with the memory array above its location”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Scheuerlein into the method of Lee to include column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays (Scheuerlein ¶ [0006]). The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of enabling a denser support circuit arrangement (Scheuerlein ¶ [0006]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827