DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE WITH A CONDUCTIVE STRUCTURE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM COMPRISING THE SEMICONDUCTOR DEVICE.
Allowable Subject Matter
Claims 4-7; and 12-20 are objected to as being dependent upon a rejected base claim (1; and 11, respectively), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 4, the prior art cannot be used to satisfy the limitations of: a second isolation structure located on a side (outer walls) of the gate structure away from the semiconductor body along the second direction, wherein the second isolation structure is in contact with a surface of the second part away from the first part, the surface of the second part close to the gate structure along the first direction, and the surface of the gate structure close to the second part along the first direction, in addition to the additionally claimed features of claims 1 and 3.
B. Re claim 5, the prior art cannot be used to satisfy the limitations of: wherein the second isolation structure comprises a first sub-structure and a second sub-structure arranged along the first direction, wherein the first sub-structure is located on the side of the gate structure away from the semiconductor body along the second direction; and the second sub-structure is located on a side of the second part away from the first part, and located between the surface of the gate structure close to the second part along the first direction and the surface of the second part close to the gate structure along the first direction, in addition to the additionally claimed features of claims 1 and 3-4.
In Re claim 7, it is objected to due to its dependence on claim 5.
C. Re claim 6, the prior art cannot be used to satisfy the limitations of: wherein the second isolation structure comprises a first sub-structure, a third sub-structure and a fourth sub-structure arranged along the first direction, wherein the first sub-structure is located on the side of the gate structure away from the semiconductor body along the second direction; the third sub-structure is located between the surface of the gate structure close to the second part along the first direction and the surface of the second part close to the gate structure along the first direction; and the fourth sub-structure is located on a side of the second part away from the first part, in addition to the additionally claimed features of claims 1 and 3-4.
D. Re claim 12, the prior art cannot be used to satisfy the limitations of: wherein the gate material layer covers part of a surface of the semiconductor pillar and covers an exposed bottom surface of the semiconductor layer and forming a first sub-structure on a side of the gate material layer away from the semiconductor pillar along the second direction, in addition to the additionally claimed features of claims 11 and 12.
E. Re claim 13, the prior art cannot be used to satisfy the limitations of: filling the third grooves with a first dielectric layer, wherein the first dielectric layer covers a remaining surface of the semiconductor pillar and covers surfaces of the gate material layer and the first sub-structure away from the bottom surface of the semiconductor layer along the first direction; and removing part of the semiconductor pillar to form a fourth groove, wherein a size of a remaining semiconductor pillar along the first direction is greater than a size of the gate material layer along the first direction, in addition to the additionally claimed features of claims 11-12.
F. Re claim 14, the prior art cannot be used to satisfy the limitations of: removing part of the first dielectric layer to form a fifth groove having a curved edge, wherein a remaining first dielectric layer constitutes a second sub-structure; and the first sub-structure and the second sub-structure constitute a second isolation structure, in addition to the additionally claimed features of claims 11-13.
In Re claims 15 and 19-20, they are objected to due to their dependence on claim 14.
G. Re claim 16, the prior art cannot be used to satisfy the limitations of: forming a fourth sub-structure on a side of the second dielectric layer away from the semiconductor pillar along the second direction; and removing part of the semiconductor pillar to form a sixth groove, wherein a size of a remaining semiconductor pillar along the first direction is greater than a size of the gate material layer along the first direction, in addition to the additionally claimed features of claims 11-12.
H. Re claim 17, the prior art cannot be used to satisfy the limitations of: removing part of the second dielectric layer to form a seventh groove having a curved edge, wherein a remaining second dielectric layer constitutes a third sub-structure; and the first sub-structure, the third sub-structure and the fourth sub-structure constitute a second isolation structure, in addition to the additionally claimed features of claims 11-12 and 16.
In Re claim 18, it is objected to due to its dependence on claim 17.
Claim Objections
Claim 12 is objected to because of the following informalities: the grammatical errors “forming a semiconductor body” and “a first direction” in lines 1-2 are presumed to be read as “forming the semiconductor body” and “the first direction” consistent with “a first direction” in line 2 of claim 11. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8, 9; 10; and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al (US 2023/0069096 A1, hereafter Yang).
Re claim 1, Yang discloses in FIG. 17 a semiconductor device (1700), comprising:
a semiconductor structure (1726; [0126]) comprising a semiconductor body (1730; [0127]) extending along a first direction (Z-direction; [0127]); and
a conductive structure (1742; [0129]) located on a side (upper surface) of the semiconductor body (1730) along the first direction (Z-direction),
wherein the conductive structure (1742) comprises a first part (lower region; see inserted figure below) and a second part (upper region; see inserted figure below) arranged along a second direction (X-direction into the page); the first part (lower region) is in contact with (physically and electrically) an end (upper surface) of the semiconductor body (1730); a size (lateral extension) of a portion (below half of vertical extension of 1742; see inserted figure below) of the first part (lower region) close to (near) the second part (upper region) in a third direction (Y-direction) is different from (not the same as) a size (lateral extension) of a portion (above half of vertical extension of 1742; see inserted figure below) of the second part (upper region) close to (near) the first part (lower region) in the third direction (Y-direction); the second direction (X-direction) intersects (crosses; see inserted figure below) the third direction (Y-direction), and the first direction (Z-direction) is perpendicular (normal) to a plane (X-Y) formed by the second direction (X-direction) and the third direction (Y-direction).
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For the record, the inserted figure (annotated Figure 17 of Yang) depicts sizes of the first and second parts of the conductive structure (1742) relative to the third direction (Y).
Re claim 2, Yang discloses the semiconductor device of claim 1, wherein the size (lateral extension) of the portion (below half of vertical extension of 1742) of the first part (lower region) close to (near) the second part (upper region) in the third direction (Y-direction) is a first size (LE1; see inserted figure above); the size (lateral extension) of the portion (above half of vertical extension of 1742) of the second part (upper region) close to (near) the first part (lower region) in the third direction (Y-direction) is a second size (LE2; see inserted figure above); and the second size (LE2) is greater (wider due to tapered shape) than the first size (LE1).
Re claim 3, Yang discloses the semiconductor device of claim 1, wherein the semiconductor structure (1726) further comprises: a gate structure (1736; [0127]) located on a side ([0136]) of the semiconductor body (1730) close to (near) the second part (upper region) in the second direction (X-direction), wherein a surface (upper plane and sidewall) of the gate structure (1736) close to (near) the second part (upper region) along the first direction (Z-direction) is spaced apart (isolated) from a surface (upper plane and sidewall) of the second part (upper region) close to (near) the gate structure (1736) along the first direction (Z-direction).
Re claim 8, Yang discloses the semiconductor device of claim 1, wherein the semiconductor structure (1726) further comprises: a capacitor structure (1728; [0128]) connected with an end (upper surface) of the conductive structure (1742) away from (above) the semiconductor body (1730) in the first direction (Z-direction).
Re claim 9, Yang discloses the semiconductor device of claim 1, further comprising: a plurality of the semiconductor structures (all 1726) arranged in an array (FIG. 18; [0126]) along the second direction (X-direction) and the third direction (Y-direction), wherein the plurality of the semiconductor structures (all 1726) arranged along the second direction (X-direction) comprise a first semiconductor structure (4th 1726) and a second semiconductor structure (5th 1726) arranged alternately (with 2nd and 3rd 1726); and the first semiconductor structure (4th 1726) and the second semiconductor structure (5th 1726) disposed adjacently constitute one semiconductor structure group (pair), wherein the first semiconductor structure (4th 1726) comprises a first semiconductor body (see claim 1), a first gate structure (see claim 3) and a first conductive structure (see claim 1); the second semiconductor structure (5th 1726) comprises a second semiconductor body (see claim 1), a second gate structure (see claim 3) and a second conductive structure (see claim 1); wherein the first gate structure (1736 of 4th 1726) is located on a side (sidewall) of the first semiconductor body (1730 of 4th 1726) close (adjacent) to the second semiconductor body (1730 of 5th 1726), and the second gate structure (1736 of 5th 1726) is located on a side (sidewall) of the second semiconductor body (1730 of 5th 1726) close (adjacent) to the first gate structure (1736 of 4th 1726), and wherein a second part (see claim 1) of the first conductive structure (1742 of 4th 1726) is located on a side of (facing) a first part (see claim 1) of the first conductive structure (1742 of 4th 1726) close (adjacent) to the second conductive structure (1742 of 5th 1726), and a second part (see claim 1) of the second conductive structure (1742 of 5th 1726) is located on a side (facing) of a first part (see claim 1) of the second conductive structure (1742 of 5th 1726) close (adjacent) to the first conductive structure (1742 of 4th 1726).
Re claim 10, Yang discloses in FIGS. 17 and 31 memory system (3102; [0191]), comprising:
a semiconductor device (1700/3104; [0192] and see claim 1), comprising:
a semiconductor structure comprising a semiconductor body extending along a first direction (see claim 1); and
a conductive structure located on a side of the semiconductor body along the first direction, wherein the conductive structure comprises a first part and a second part arranged along a second direction; the first part is in contact with an end of the semiconductor body; a size of a portion of the first part close to the second part in a third direction is different from a size of a portion of the second part close to the first part in the third direction; the second direction intersects the third direction, and the first direction is perpendicular to a plane formed by the second direction and the third direction (see claim 1); and
a memory controller (3106; [0191]) connected with the semiconductor device (1700/3104) and configured to control ([0193]) the semiconductor device (1700/3104).
Re claim 11, Yang discloses in FIGS. 17 and 19A-19M a method of manufacturing a semiconductor device (1700; [0194]), comprising:
forming a semiconductor body extending along a first direction (see claim 1 and [0305]-[0327]); and
forming a conductive structure located on a side of the semiconductor body along the first direction (see claim 1 and [0305]-[0327]),
the semiconductor body (1730/1920) and the conductive structure (1742) being configured to form a semiconductor structure (1700; see claim 1 and [0305]-[0327]),
wherein the conductive structure comprises a first part and a second part arranged along a second direction; the first part is in contact with an end of the semiconductor body; a size of a portion of the first part close to the second part in a third direction is different from a size of a portion of the second part close to the first part in the third direction; the second direction intersects the third direction, and the first direction is perpendicular to a plane formed by the second direction and the third direction (see claim 1 and [0305]-[0327]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US-11373914-B2 and US-10998440-B2 disclose gate material layers, isolation layers and/or dielectric layers on surfaces of semiconductor bodies.
US-10886278-B2 discloses two-part conductive features with a first part having a different size than a size of a second part.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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