Prosecution Insights
Last updated: May 29, 2026
Application No. 18/790,667

INSERT INSERTED TO TRAY FOR TRANSPORTING SEMICONDUCTOR PRODUCTS, TRAY INCLUDING THE INSERT, AND SEMICONDUCTOR PRODUCT TEST SYSTEM INCLUDING THE INSERT

Non-Final OA §102
Filed
Jul 31, 2024
Priority
May 21, 2024 — RE 10-2024-0065951
Examiner
ASTACIO-OQUENDO, GIOVANNI
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ateco Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
640 granted / 724 resolved
+20.4% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
17 currently pending
Career history
735
Total Applications
across all art units

Statute-Specific Performance

§101
13.5%
-26.5% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
4.7%
-35.3% vs TC avg
§112
30.6%
-9.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 724 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1 – 16 are pending. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 – 2 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Na et al. (US 2009/0245982 A1; hereinafter Na). Regarding Claim 1, Na discloses a test tray (para[0007]; a side sectional view illustrating an insert and an insert opening unit for a test tray) for testing a semiconductor product (Fig. 1, item 1) , comprising: PNG media_image1.png 408 466 media_image1.png Greyscale a tray (Fig. 1 and para[0008]; an insert 10 of a test tray includes a housing 11); and an insert (Fig. 1, item 10) comprising an accommodating portion (Fig. 1, item 11a) configured to accommodate the semiconductor product (Fig. 1, item 1), and inserted into the tray (Fig. 1 and para [0008]; an insert 10 of a test tray includes a housing 11 having an accommodating space 11a into which a semiconductor device 1 is accommodated); and wherein the accommodating portion (Fig. 1, item 11a) having a first posture at a first angle to the tray to accommodate the semiconductor product (Fig. 1 and para [0011]; holding member 12a includes one side coupled to the hinge hole lid of the housing 11 by a hinge pin 12d and the opposite side protruding toward the accommodating space 11a to be rotated about the hinge pin 12d; the upper surface of the holding member 12a forms a curved surface in the lateral direction of the accommodating space 11a, and a locking step 12e is formed on the curved surface), and a second posture at a second angle to the tray to test the semiconductor product (Fig. 1 and para [0012]; the locking member 12b, a spring supporting protrusion 12f corresponding to the spring fixing protrusion 11c is formed at an upper portion thereof, and the ends of the spring 12c are fixed to the spring fixing protrusion 11c and the spring supporting protrusion 12f to be elastically supported and moved upward and downward within the installing space 11b). Regarding Claim 2, Na discloses the test tray of claim 1, wherein the insert (Fig. 1, item 10) further comprises a mounting portion (Fig. 1, item 20) mounted to the tray and supporting the accommodating portion (Fig. 1, item 11a) adjustable in angle to the tray (Fig. 1 and para [0017]; when a test tray is transferred and is stopped at a preset position, the insert opening unit 20 is raised and the position determining protrusions 21 are inserted into the position determining holes 11f of the housing 11 so that a proper position between the insert opening unit 20 and the insert 10 is determined). Allowable Subject Matter Claims 3 – 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 3, the prior art of record does not teach claimed limitation: “wherein the accommodating portion comprises a rotary body formed with a mounting slot to accommodate the semiconductor product and supported to be adjustable in angle on the mounting portion” in combination with all other claimed limitations of claim 3. Regarding Claims 4 – 13, the claims would be allowable as they further limit claim 3. Claims 14 – 16 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding Claim 14, the prior art of record does not teach claimed limitation: “the insert comprising a first type insert that accommodates the first type semiconductor product therein and exposes a lower end of the first type semiconductor product to a lower side of the tray, and a second type insert that accommodates the second type semiconductor product therein and has a first posture where an entrance through which the second type semiconductor product enters and exits is exposed to an upper side of the tray and a second posture where a lateral side of the accommodated second type semiconductor product is exposed to a lower side of the tray, and the tray allowing the first type insert or the second type insert to be selectively inserted thereto” in combination with all other claimed limitations of claim 14. Regarding Claim 15, the prior art of record does not teach claimed limitation: “the accommodating portion having a first posture where an entrance of the mounting slot is exposed to an upper external space of the mounting portion, and a second posture where the mounting slot is exposed to a lower external space of the mounting portion” in combination with all other claimed limitations of claim 15. Regarding Claim 16, the prior art of record does not teach claimed limitation: “a posture switching unit configured to switch the posture of the insert by pressurizing one side of the insert to change an angle of the insert” in combination with all other claimed limitations of claim 16. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Ranganathan et al. (US 12,174,248 B2) teaches a tester rack comprising a plurality of slots wherein at least one slot in the tester rack is a dedicated slot operable to receive a carrier from a rear position of the tester rack, wherein the rear position of the tester rack is opposite a forward position of a tester rack, wherein the forward position of the tester rack faces a handler and a front-facing elevator, wherein the carrier comprises an array of DUTs, wherein each DUT in the array of DUTs aligns with a respective socket of a plurality of sockets disposed on a test interface board (TIB) operable to be affixed in an available slot of the plurality of slots (see claim 10). Arai et al. (US 11,579,189 B2) discloses an electronic component handling apparatus that handles a device under test (DUT), the electronic component handling apparatus comprising: transfer units that each comprise a DUT transfer part that transfers the DUT between a first tray and a second tray; multiple contact units that adjust a temperature of the DUT independently from one another and press the DUT against a socket independently from one another, each of the multiple contact units pressing the DUT mounted on the first tray against the socket; and a tray transporter that transports the first tray between the transfer units and the multiple contact units, wherein the socket is disposed on a test head that is mounted to each of the multiple contact units and that is connected to a tester, the multiple contact units each comprise: a thermal stress applying section that accommodates the first tray and that applies a thermal stress to the DUT mounted on the first tray; a pressing section that presses the DUT mounted on the first tray against the socket (see claim 1). Horino et al. (US 11,714,124 B2) suggests an electronic component handling apparatus that handles a device under test (DUT), the electronic component handling apparatus comprising: multiple transfer units that each comprise a DUT transfer part that mounts the DUT on a first tray or that removes the DUT from the first tray; multiple contact units that each press the DUT mounted on the first tray against a socket disposed on a test head connected to a tester; and a tray transporter that transports the first tray between the multiple contact units and the multiple transfer units (see claim 1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to GIOVANNI ASTACIO-OQUENDO whose telephone number is (571)270-5724. The examiner can normally be reached Monday - Friday, 8:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 3/7/2026
Read full office action

Prosecution Timeline

Jul 31, 2024
Application Filed
Mar 11, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+10.4%)
2y 5m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 724 resolved cases by this examiner. Grant probability derived from career allowance rate.

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