DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-17 are present for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 4, 13 & 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4, on last 3 lines, “said control signals” lack a clear antecedent basis from parent claim 1. Please amend it to read as “said one or more control signals” to be consistent with language of claim 1.
Claim 13, line 1, “the digital detector” lacks a clear antecedent basis from parent claim 1. Please amend it to read “the first digital detector” to be consistent with language of claim 1.
Claim 15, line 3, the term “the digital detector” similarly needs a clear antecedent basis.
Allowable Subject Matter
3. Claims 1-3 , 5-12, 14. 16-17 all contain allowable subject matter over the prior arts of record for reciting a novel “in-memory computation device” (IMC) device configured to receive an input signal indicative of a plurality of input values and to provide at least an output signal indicative of a plurality of output values, the IMC device comprising the following components:
- a word line activation circuit configured to receive the input signal and to provide a plurality of word line activation signals, each word line activation signal being a function of a respective input value of the input values;
- a biasing circuit configured to provide a biasing voltage;
- a memory array comprising a plurality of first memory cells coupled to a first bit line and each coupled to a respective word line, the first bit line being configured to receive the biasing voltage, the first memory cells being configured to each store a respective computational weight and to each receive from the respective word line a respective word line activation signal of the plurality of word line activation signals, the first memory cells being configured to be each traversed by a respective cell current which is a function of the biasing voltage, of the respective word line activation signal and of the respective computational weight, the first bit line being configured to be traversed by a first bit line current which is a sum of the cell currents; and
- a first digital detector coupled to the first bit line and configured to sample the first bit line current and, in response to the first bit line current, provide the output signal; wherein the first digital detector comprises: and
- a control stage electrically coupled to the first bit line and configured to receive the first bit line current, generate at least a first main control mirrored current in response to the first bit line current, compare the first main control mirrored current with at least a first reference current and generate one or more control signals indicative of said comparison; and
- a selection stage electrically coupled to the control stage and the first bit line and configured to receive the first bit line current and the one or more control signals and generate a total selection current in response to the first bit line current and as a function of the one or more control signals; and
- an integration stage electrically coupled to the selection stage and configured to receive and sample the total selection current; and
- a charge counter stage electrically coupled to the integration stage and to the control stage and configured to receive the total selection current sampled and the one or more control signals and generate, as a function of the one or more control signals, the output signal in response to the sampled first total selection current.
Additionally, the claims 4, 13 & 15 are objected as dependent upon rejected claim 1 but they also add more novel libations to the recited structure of parent claim 1, which they are also together allowed for the same reason above.
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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