DETAILED ACTION
This action is responsive to the following communications: the Application filed on July 31, 2024.
Claims 1-20 are pending. Claims 1, 10 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 10 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 20140313819).
Regarding independent claim 1, Choi et al. disclose a memory instance [Fig. 1: 100], comprising:
a first memory [Fig. 1: SRAM 140] comprising a first bitcell array [Fig. 1: 146] and first peripheral circuitry [Fig. 1: 144, para. 31-32];
a bitcell array power supply [Fig. 1: 110] providing a first bitcell array power supply fixed voltage [the first power circuit 110 generates a cell driving voltage VDDCE that is a voltage for driving memory cells of the SRAM 14, para. 27. The first power circuit 110 generates the cell driving voltage VDDCE with a level that is constant regardless of a performance mode P_Mode, para. 36];
a first peripheral logic power supply [Fig. 1: 120] providing a first peripheral logic power supply variable voltage [Fig. 1: VDDPE] to first peripheral circuitry [the second power circuit 120 generates a peripheral driving voltage VDDPE that is a voltage for driving control circuits except for the memory cells of the SRAM 140, para. 28. The second power circuit 120 generates the peripheral driving voltage VDDPE with a level which is variable according to the performance mode P_Mode, para. 37]; and
a first power multiplexer [Fig. 1: 142] operable to provide a higher of the first bitcell array power supply fixed voltage and the first peripheral logic power supply variable voltage to the first bitcell array [the auto power switch 142 selects the higher of a cell driving voltage VDDCE and a peripheral driving voltage VDDPE supplied to an SRAM 140 at a high-speed mode, para. 41].
Regarding claim 8, Choi et al. disclose the first power multiplexer [Fig. 1: 142] further comprises a first overdrive enable input operable to receive an indication of whether the first peripheral logic power supply is at a voltage higher than the first bitcell array power supply fixed voltage, the received first overdrive enable input operable to cause the first power multiplexer to provide the higher of the first bitcell array power supply fixed voltage and the first peripheral logic power supply variable voltage to the first bitcell array [see Fig. 3, the cell driving voltage VDDCE and the peripheral driving voltage VDDPE supplied through power lines 114 and 124 have substantially the same or different levels from each other according to a performance mode P_Mode. The auto power switch 142 selects the higher of a cell driving voltage VDDCE and a peripheral driving voltage VDDPE supplied to an SRAM 140 at a high-speed mode, para. 41-42]
Regarding independent claim 10, Choi et al. disclose a method of providing power to a memory [para. 6], comprising:
providing a bitcell array power signal at a bitcell array power signal fixed voltage to a first power multiplexer [the first power circuit 110 generates a cell driving voltage VDDCE that is a voltage for driving memory cells of the SRAM 14 through the auto power switch 142, para. 27 as well as para. 53. The first power circuit 110 generates the cell driving voltage VDDCE with a level that is constant regardless of a performance mode P_Mode, para. 36];
providing a first peripheral logic power signal at a first peripheral logic power supply variable voltage to a first peripheral circuitry of a first memory and to the first power multiplexer [the second power circuit 120 generates a peripheral driving voltage VDDPE that is a voltage for driving control circuits except for the memory cells of the SRAM 140 through the auto power switch 142, para. 28, as well as para. 53. The second power circuit 120 generates the peripheral driving voltage VDDPE with a level which is variable according to the performance mode P_Mode, para. 37]; and
providing, via the first power multiplexer, a higher of the bitcell array power signal fixed voltage and the first peripheral logic power supply variable voltage to a first bitcell array of the first memory [the auto power switch 142 selects the higher of a cell driving voltage VDDCE and a peripheral driving voltage VDDPE supplied to an SRAM 140 at a high-speed mode, para. 41].
Regarding claim 17, Choi et al. disclose further comprising receiving a first overdrive enable input in the first power multiplexer indicating whether the first peripheral logic power signal is at a voltage higher than the bitcell array power signal fixed voltage [see Fig. 3, the cell driving voltage VDDCE and the peripheral driving voltage VDDPE supplied through power lines 114 and 124 have substantially the same or different levels from each other according to a performance mode P_Mode, para. 42. When the performance mode P_Mode is a high-speed mode, the peripheral driving voltage VDDPE boosted may be rendered higher than the cell driving voltage VDDCE, para. 31].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 9, 11-14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20140313819) as applied to claims 1 and 10 above, in view of Chakraborty et al. (US 20120324250).
Regarding claim 2, Choi et al. teach the limitations with respect to claim 1.
However, Choi et al. are silent with respect to further comprising:
a second memory comprising a second bitcell array and second peripheral circuitry, the bitcell array power supply providing a second bitcell array power supply fixed voltage;
a second peripheral logic power supply providing a second peripheral logic power supply variable voltage to the second peripheral circuitry, the second peripheral logic power supply variable voltage to be different from the first peripheral logic power supply variable voltage; and
a second power multiplexer operable to provide a higher of the second bitcell array power supply fixed voltage and the second peripheral logic power supply variable voltage to the second bitcell array.
Chakraborty et al. teach a clustered multicore processor 101 included a first core 105 has a first architecture and is designed for a first voltage-frequency domain and a second core 105 has the same first architecture and is designed for a second voltage-frequency domain [see Fig. 3, para. 45-46]. Chakraborty et al. also discuss multicore arrangements including L1-L2 caches.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Chakraborty et al. to the teachings of Choi et al. such that implementing a second memory instance for the second core of Chakraborty et al. using the same dual rail SRAM of Choi et al. to increase performance and reduce power consumption [see Chakraborty et al.’s para. 46].
Regarding claim 3, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 2.
Furthermore, Chakraborty et al. disclose wherein the first memory is associated with a first processor core in a computer system operating at a first performance level and the second memory is associated with a second processor core in the computer system operating at a second performance level [see Fig. 3, a first core 105 has a first architecture and is designed for a first voltage-frequency domain. A second core 105 has the same first architecture and is designed for a second voltage-frequency domain. As a result, processing tasks may be allocated to either the first core 105 or the second core 105 to increase performance, para. 46. If the utilization rate of the core 105 falls below the lower utilization threshold, the allocation module 130 allocates 575 the processing task to a core 105 with a lower voltage-frequency domain 610, 615 and lower power consumption. If the utilization rate of the core 105 exceeds the upper utilization threshold, the allocation module 130 allocates 580 the processing task to a core 105 with a higher voltage-frequency domain 610, 615 and increased performance, para. 76].
Regarding claim 4, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 3.
Furthermore, Chakraborty et al. disclose further comprising multiple memories and associated processors at the first performance level, multiple memories and associated processors at the second performance level, or a combination thereof [see Fig. 3, a clustered multicore processor 101 including 4 clusters 120 with each one is depicted with two on-chip cores 105, para. 45. Cores 105 may share both L1 caches 110. L2 caches 115 may be shared between clusters 120, para. 47. A first core 105 has a first architecture and is designed for a first voltage-frequency domain. A second core 105 has the same first architecture and is designed for a second voltage-frequency domain, para. 46. More than one core can have the same voltage-frequency domain assigned, para. 37].
Regarding claim 5, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 2.
Choi et al. disclose one memory [Fig. 1: 100] comprising a bitcell array [Fig. 1: 146], a peripheral circuitry [Fig. 1: 144], and an power multiplexer [Fig. 1: 142]; the peripheral circuitry [Fig. 1: 144] coupled to one of the first peripheral logic power supply [Fig. 1: 110] and the second peripheral logic power supply [Fig. 1: 120], the power multiplexer [Fig. 1: 142] operable to provide a higher of the bitcell array power supply fixed voltage [the auto power switch 142 selects the higher of a cell driving voltage VDDCE and a peripheral driving voltage VDDPE supplied to an SRAM 140 at a high-speed mode, para. 41], and the one of the first peripheral logic power supply and the second peripheral logic power supply coupled to the peripheral circuitry to the bitcell array [see Fig. 3, para. 41-42].
Chakraborty et al. disclose a clustered multicore processor 101 included a first core 105 has a first architecture and is designed for a first voltage-frequency domain and a second core 105 has the same first architecture and is designed for a second voltage-frequency domain [see Fig. 3, para. 45-46]. Chakraborty et al. also discuss multicore arrangements including L1-L2 caches.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Chakraborty et al. to the teachings of Choi et al. such that implementing an additional memory instance for the other core of Chakraborty et al. using the same dual rail SRAM of Choi et al. to increase performance and reduce power consumption [see Chakraborty et al.’s para. 46].
Regarding claim 9, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 2.
Furthermore, Choi et al. disclose the first power multiplexer further comprises a first overdrive enable input operable to receive an indication of whether the first peripheral logic power supply variable voltage is at a voltage higher than the first bitcell array power supply fixed voltage [see Fig. 3, the cell driving voltage VDDCE and the peripheral driving voltage VDDPE supplied through power lines 114 and 124 have substantially the same or different levels from each other according to a performance mode P_Mode, para. 42. When the performance mode P_Mode is a high-speed mode, the peripheral driving voltage VDDPE boosted may be rendered higher than the cell driving voltage VDDCE, para. 31].
However, Choi et al. are silent with respect to the second power multiplexer further comprises a second overdrive enable input operable to receive an indication of whether the second peripheral logic power supply variable voltage is at a voltage higher than the second bitcell array power supply fixed voltage.
Chakraborty et al. disclose a clustered multicore processor 101 included a first core 105 has a first architecture and is designed for a first voltage-frequency domain and a second core 105 has the same first architecture and is designed for a second voltage-frequency domain [see Fig. 3, para. 45-46]. Chakraborty et al. also discuss multicore arrangements including L1-L2 caches.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Chakraborty et al. to the teachings of Choi et al. such that implementing a second memory instance for the second core of Chakraborty et al. using the same dual rail SRAM of Choi et al. that included a second power multiplexer further comprises a second overdrive enable input operable to receive an indication of whether the second peripheral logic power supply variable voltage is at a voltage higher than the second bitcell array power supply fixed voltage as taught by Choi et al. to increase performance and reduce power consumption [see Chakraborty et al.’s para. 46].
Regarding claim 11, Choi et al. teach the limitations with respect to claim 10.
However, Choi et al. are silent with respect to further comprising:
providing a second peripheral logic power signal at a second peripheral logic power supply variable voltage to a second peripheral circuitry of a second memory and to a second power multiplexer; and
providing, via the second power multiplexer, a higher of the bitcell array power signal fixed voltage and the second peripheral logic power supply variable voltage to a second bitcell array of the second memory.
Chakraborty et al. teach a clustered multicore processor 101 included a first core 105 has a first architecture and is designed for a first voltage-frequency domain and a second core 105 has the same first architecture and is designed for a second voltage-frequency domain [see Fig. 3, para. 45-46]. Chakraborty et al. also discuss multicore arrangements including L1-L2 caches.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Chakraborty et al. to the teachings of Choi et al. such that implementing a second memory instance for the second core of Chakraborty et al. using the same dual rail SRAM of Choi et al. to increase performance and reduce power consumption [see Chakraborty et al.’s para. 46].
Regarding claim 12, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 11.
Furthermore, Chakraborty et al. disclose wherein the first memory is associated with a first processor core in a computer system operating at a first performance level and the second memory is associated with a second processor core in the computer system operating at a second performance level [see Fig. 3, a first core 105 has a first architecture and is designed for a first voltage-frequency domain. A second core 105 has the same first architecture and is designed for a second voltage-frequency domain. As a result, processing tasks may be allocated to either the first core 105 or the second core 105 to increase performance, para. 46. If the utilization rate of the core 105 falls below the lower utilization threshold, the allocation module 130 allocates 575 the processing task to a core 105 with a lower voltage-frequency domain 610, 615 and lower power consumption. If the utilization rate of the core 105 exceeds the upper utilization threshold, the allocation module 130 allocates 580 the processing task to a core 105 with a higher voltage-frequency domain 610, 615 and increased performance, para. 76].
Regarding claim 13, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 12.
Furthermore, Chakraborty et al. disclose further comprising providing multiplexed power to multiple memories and associated processors at first performance level, multiple memories and associated processors at second performance level, or a combination thereof [see Fig. 3, a clustered multicore processor 101 including 4 clusters 120 with each one is depicted with two on-chip cores 105, para. 45. Cores 105 may share both L1 caches 110. L2 caches 115 may be shared between clusters 120, para. 47. A first core 105 has a first architecture and is designed for a first voltage-frequency domain. A second core 105 has the same first architecture and is designed for a second voltage-frequency domain, para. 46. More than one core can have the same voltage-frequency domain assigned, para. 37].
Regarding claim 14, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 11.
Choi et al. disclose further comprising:
providing a higher of the bitcell array power signal fixed voltage and a selected one of the first peripheral logic power signal and the second peripheral logic power signal to at least one bitcell array of at least one memory [the auto power switch 142 selects the higher of a cell driving voltage VDDCE and a peripheral driving voltage VDDPE supplied to an SRAM 140 at a high-speed mode, para. 41], a peripheral circuitry of the at least one memory coupled to the selected one of the first peripheral logic power signal and the second peripheral logic power signal [see Fig. 1, para. 28].
Chakraborty et al. disclose a clustered multicore processor 101 included a first core 105 has a first architecture and is designed for a first voltage-frequency domain and a second core 105 has the same first architecture and is designed for a second voltage-frequency domain [see Fig. 3, para. 45-46]. Chakraborty et al. also discuss multicore arrangements including L1-L2 caches.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Chakraborty et al. to the teachings of Choi et al. such that implementing an additional memory instance for the other core of Chakraborty et al. using the same dual rail SRAM of Choi et al. to increase performance and reduce power consumption [see Chakraborty et al.’s para. 46].
Regarding claim 18, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claim 11.
Furthermore, Choi et al. disclose further comprising receiving an indication of whether the first peripheral logic power supply variable voltage is at a voltage higher than the bitcell array power signal fixed voltage in the first power multiplexer [see Fig. 3, the cell driving voltage VDDCE and the peripheral driving voltage VDDPE supplied through power lines 114 and 124 have substantially the same or different levels from each other according to a performance mode P_Mode, para. 42. When the performance mode P_Mode is a high-speed mode, the peripheral driving voltage VDDPE boosted may be rendered higher than the cell driving voltage VDDCE, para. 31].
However, Choi et al. are silent with respect to receiving an indication of whether the second peripheral logic power supply variable voltage is at a voltage higher than the bitcell array power signal fixed voltage in the second power multiplexer.
Chakraborty et al. disclose a clustered multicore processor 101 included a first core 105 has a first architecture and is designed for a first voltage-frequency domain and a second core 105 has the same first architecture and is designed for a second voltage-frequency domain [see Fig. 3, para. 45-46]. Chakraborty et al. also discuss multicore arrangements including L1-L2 caches.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Chakraborty et al. to the teachings of Choi et al. such that implementing a second memory instance for the second core of Chakraborty et al. using the same dual rail SRAM of Choi et al. that included a second power multiplexer further comprises a second overdrive enable input operable to receive an indication of whether the second peripheral logic power supply variable voltage is at a voltage higher than the second bitcell array power supply fixed voltage as taught by Choi et al. to increase performance and reduce power consumption [see Chakraborty et al.’s para. 46].
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20140313819) as applied to claims 1 and 10 above, in view of Cao et al. (US 20120324250).
Regarding claims 6 and 15, Choi et al. teach the limitations with respect to claims 1 and 10.
Furthermore, Choi et al. disclose the first power multiplexer configured to avoid a direct current path between the bitcell array power supply and the first peripheral logic power supply [see Fig. 4, when activated, the comparator 143 compares the peripheral driving voltage VDDPE with the cell driving voltage VDDCE. When the peripheral driving voltage VDDPE is higher than the cell driving voltage VDDCE, the comparator 143 outputs a low-level signal. The first PMOS transistor PM1 is turned on, and the second PMOS transistor is turned off. Thus, the peripheral driving voltage VDDPE, which is relatively higher than the cell driving voltage, is provided as a cell voltage VDDC. When the peripheral driving voltage VDDPE is equal to or lower than the cell driving voltage VDDCE, the comparator 143 outputs a high-level signal. The first PMOS transistor PM1 is turned off, and the second PMOS transistor is turned on. Thus, the cell driving voltage VDDCE, which is relatively higher than the peripheral driving voltage VDDPE, is provided as the cell voltage VDDC, para. 45].
However, Choi et al. are silent with respect to the first power multiplexer comprises a digital circuit.
Cao et al. teach the power multiplexer [Fig. 3: 310] comprises a digital circuit [a head switch is connected between a power rail that is serving as a voltage source and a load performing digital processing. The head switch 214 includes multiple power-mux, para. 45-46] configured to avoid a direct current path between the bitcell array power supply and the first peripheral logic power supply [the power-mux circuitry 310 provides a means for preventing a short-circuit current between the first power rail 202 and the second power rail 204, para. 50].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Cao et al. to the teachings of Choi et al. such that incorporating the power multiplexer comprises a digital circuit configured to avoid a direct current path between the bitcell array power supply and the first peripheral logic power supply as taught by Cao et al. into the dual rail SRAM of Choi et al. to prevent a short-circuit current between the different power rails and reduce power consumption.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20140313819) in view of Chakraborty et al. (US 20120324250) as applied to claims 2 and 12 above and further in view of Cao et al. (US 20120324250).
Regarding claims 7 and 16, Choi et al. in combination with Chakraborty et al. teach the limitations with respect to claims 2 and 11.
Furthermore, Choi et al. disclose the first power multiplexer configured to avoid a direct current path between the bitcell array power supply and the first peripheral logic power supply [see Fig. 4, when activated, the comparator 143 compares the peripheral driving voltage VDDPE with the cell driving voltage VDDCE. When the peripheral driving voltage VDDPE is higher than the cell driving voltage VDDCE, the comparator 143 outputs a low-level signal. The first PMOS transistor PM1 is turned on, and the second PMOS transistor is turned off. Thus, the peripheral driving voltage VDDPE, which is relatively higher than the cell driving voltage, is provided as a cell voltage VDDC. When the peripheral driving voltage VDDPE is equal to or lower than the cell driving voltage VDDCE, the comparator 143 outputs a high-level signal. The first PMOS transistor PM1 is turned off, and the second PMOS transistor is turned on. Thus, the cell driving voltage VDDCE, which is relatively higher than the peripheral driving voltage VDDPE, is provided as the cell voltage VDDC, para. 45].
However, Choi et al. are silent with respect to the first power multiplexer comprises a digital circuit and the second power multiplexer comprises a digital circuit configured to avoid a direct current path between the bitcell array power supply and the second peripheral logic power supply.
Cao et al. teach the power multiplexer [Fig. 3: 310] comprises a digital circuit [a head switch is connected between a power rail that is serving as a voltage source and a load performing digital processing. The head switch 214 includes multiple power-mux, para. 45-46] configured to avoid a direct current path between the bitcell array power supply and the first peripheral logic power supply [the power-mux circuitry 310 provides a means for preventing a short-circuit current between the first power rail 202 and the second power rail 204, para. 50].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Cao et al. to the teachings of Choi et al. in combination with Chakraborty et al. such that incorporating the power multiplexers comprise a digital circuit configured to avoid a direct current path between the bitcell array power supply and the first peripheral logic power supply as taught by Cao et al. into the dual rail SRAMs of Choi et al. in combination with Chakraborty et al. to prevent a short-circuit current between the different power rails and reduce power consumption.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20140313819) in view of Lencioni (US 20040217798).
Regarding claim 19, Choi et al. disclose a power multiplexer [Fig. 3: 142], comprising:
an overdrive input operable to receive an indication of whether a first power voltage is higher than a second power voltage, the overdrive input driven at the second power voltage [see Fig. 4, the comparator 143 compares a peripheral driving voltage VDDPE with a cell driving voltage VDDCE. When the peripheral driving voltage VDDPE is higher than the cell driving voltage VDDCE, the comparator 143 outputs a low-level signal. When the peripheral driving voltage VDDPE is equal to or lower than the cell driving voltage VDDCE, the comparator 143 outputs a high-level signal, para. 45];
a first switch [Fig. 4: PM1] coupled to receive the first power voltage and the overdrive input, the first switch configured to selectively provide the first power voltage to an output based at least in part on the overdrive input [when the peripheral driving voltage VDDPE is higher than the cell driving voltage VDDCE, the comparator 143 outputs a low-level signal. The first PMOS transistor PM1 is turned on, and the second PMOS transistor PM2 is turned off. Thus, the peripheral driving voltage VDDPE, which is relatively higher than the cell driving voltage, is provided as a cell voltage VDDC, para. 45]; and
a second switch [Fig. 4: PM2] coupled to receive the second power voltage and the inverted level-shifted overdrive input, the second switch configured to selectively provide the second power voltage to the output based at least in part on inverted level-shifted overdrive input [when the peripheral driving voltage VDDPE is equal to or lower than the cell driving voltage VDDCE, the comparator 143 outputs a high-level signal. The first PMOS transistor PM1 is turned off, and the second PMOS transistor PM2 is turned on. Thus, the cell driving voltage VDDCE, which is relatively higher than the peripheral driving voltage VDDPE, is provided as the cell voltage VDDC, para. 45].
However, Choi et al. are silent with respect to a level shifter operable to receive the overdrive input and to provide an inverted level-shifted overdrive input driven at the first power voltage.
Lencioni teaches a level shifter [Fig. 2: 20] operable to receive the overdrive input and to provide an inverted level-shifted overdrive input driven at the first power voltage [For level shifter circuit 20, input signals IN switch from 0 V to VDD1 and output signals OUT switch from 0 V to VDD2, accordingly. When input signal IN switches from a logical 1 to a logical 0, a logical 1 (i.e., VDD2) occurs at output OUT, and a logical 0 (i.e., GND) occurs at complementary output /OUT. When input signal IN switches from a logical 1 to a logical 0, a logical 0 (i.e., GND) occurs at output OUT, and a logical 1 (i.e., VDD2) occurs at complementary output /OUT, para. 25-27].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Lencioni to the teachings of Choi et al. such that modify the power multiplexer of Choi et al. to include a level shifter as taught by Lencioni to ensure the signals applied to the switches achieve proper logic levels in the destination supply domain.
Regarding claim 20, Choi et al. in combination with Lencioni teach the limitations with respect to claim 19.
Furthermore, Choi et al. disclose wherein the power multiplexer lacks a direct current path between the first power voltage and the second power voltage [see Fig. 4 with respect to Fig. 3, when activated, the comparator 143 compares the peripheral driving voltage VDDPE with the cell driving voltage VDDCE. When the peripheral driving voltage VDDPE is higher than the cell driving voltage VDDCE, the comparator 143 outputs a low-level signal. The first PMOS transistor PM1 is turned on, and the second PMOS transistor is turned off. Thus, the peripheral driving voltage VDDPE, which is relatively higher than the cell driving voltage, is provided as a cell voltage VDDC. When the peripheral driving voltage VDDPE is equal to or lower than the cell driving voltage VDDCE, the comparator 143 outputs a high-level signal. The first PMOS transistor PM1 is turned off, and the second PMOS transistor is turned on. Thus, the cell driving voltage VDDCE, which is relatively higher than the peripheral driving voltage VDDPE, is provided as the cell voltage VDDC, para. 45].
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825