DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-25 have been amended.
Claims 1-25 have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 11-25 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 5,832,533 by Agarwal et al. (hereinafter referred to as “Agarwal”) in view of US Publication No. 2015/0089139 by Zaks et al. (previously cited and hereinafter referred to as “Zaks”).
Regarding claims 1, 13, 18, 23, and 24, taking claim 1 as representative, Agarwal discloses:
a computer program product comprising: a set of one or more computer-readable storage media; and program instructions, collectively stored in the set of one or more computer-readable storage media, for causing at least one computing device to perform computer operations including: executing an instruction within a computing environment, the instruction using one or more registers, and… multiple base- displacement pairs used to obtain multiple operands of the instruction, the executing the instruction including (Agarwal discloses, at Figure 1 and related description, a superscalar execution system including a vector processor, which discloses a computer program product comprising computer readable storage media storing instructions and causing a computing device to execute instructions including obtaining operands. Agarwal also discloses, at Figure 4 and related description, the instruction includes operand fields that specify registers. See, e.g., col. 7, lines 1-6, which describes, e.g., operand field 306 specifies a source register.)
retrieving …the multiple base-displacement pairs, the multiple base-displacement pairs …used to provide multiple operands of the instruction (Agarwal discloses, at Figure 4 and related description, obtaining multiple operands using the multiple base-displacement pairs.);
determining from the multiple base-displacement pairs the multiple operands of the instruction (Agarwal discloses, at Figure 4 and related description, determining the operands using the multiple base displacement pairs.); and
performing one or more operations of the instruction using one or more operands of the multiple operands of the instruction to obtain a result of the instruction (Agarwal discloses, at Figure 4 and related description, performing the instruction using the operands.).
Agarwal does not explicitly disclose wherein the aforementioned multiple base-displacement pairs are included in a single register.
However, in the same field of endeavor (e.g., processing instructions) Zaks discloses:
a single register that stores multiple addresses (Zaks discloses, at ¶ [0063], a single vector register that stores multiple addresses.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal to include storing the multiple base-displacement pairs, i.e., addresses, in a single register, as disclosed by Zaks, because referring to multiple operands using a single reference is a well-known aspect of parallel processing that allows increased performance due to more efficient programming.
Regarding claims 2, 14, and 19, taking claim 2 as representative, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
a base-displacement pair of the multiple base-displacement pairs includes an indication of a base register plus a displacement value (Agarwal discloses, at Figure 4 and related description, combining the base and offset, which discloses an indication of a base register plus a displacement value.).
Regarding claims 3, 15, and 20, taking claim 3 as representative, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
each base-displacement pair of the multiple base-displacement pairs includes an indication of a base register plus a displacement value. (Agarwal discloses, at Figure 4 and related description, combining the base and offset, which discloses that each pair includes an indication of a base register plus a displacement value.).
Regarding claim 4, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
…multiple base-displacement pairs. (Agarwal discloses, at Figure 4 and related description, multiple base-displacement pairs.).
Agarwal does not explicitly disclose wherein the aforementioned multiple base-displacement pairs are explicitly specified within the single register.
However, in the same field of endeavor (e.g., processing instructions) Zaks discloses:
a single register that stores multiple addresses (Zaks discloses, at ¶ [0063], a single vector register that stores multiple addresses.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal to include storing the multiple base-displacement pairs, i.e., addresses, in a single register, as disclosed by Zaks, because referring to multiple operands using a single reference is a well-known aspect of parallel processing that allows increased performance due to more efficient programming.
Regarding claim 5, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
a base-displacement pair of the multiple base-displacement pairs provides a resulting value, the resulting value being an address indicating a location of an operand of the multiple operands (Agarwal discloses, at Figure 4 and related description, combining the base and offset to generate an address, which discloses base-displacement pairs to determine an address indicating a location of operands.).
Regarding claim 6, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
a base-displacement pair of the multiple base-displacement pairs provides a resulting value, the resulting value being an operand of the multiple operands (Agarwal discloses, at Figure 4 and related description, combining the base and offset to generate an address, which discloses base-displacement pairs being an operand, e.g., in the case of a memory operation.).
Regarding claims 7, 16, and 21, taking claim 7 as representative, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
… an operand field of the instruction… the multiple base-displacement pairs (Agarwal discloses, at Figure 4 and related description, an operand field and multiple base-displacement pairs.).
Agarwal does not explicitly disclose wherein the aforementioned operand field includes the single register and the aforementioned multiple base-displacement pairs included in the single register.
However, in the same field of endeavor (e.g., processing instructions) Zaks discloses:
an operand field that designates a single register that stores multiple addresses (Zaks discloses, at ¶ [0060] et seq., an operand field that designates a single vector register that stores multiple addresses.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal to include storing the multiple base-displacement pairs, i.e., addresses, in a single register, as disclosed by Zaks, because referring to multiple operands using a single reference is a well-known aspect of parallel processing that allows increased performance due to more efficient programming.
Regarding claims 8, 17, 22, and 25, taking claim 8 as representative, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
a base-displacement pair of the multiple base-displacement pairs indicates an operand location from which to retrieve an operand of the multiple operands, and wherein the executing the instruction further includes retrieving from the operand location determined from the base-displacement pair of the multiple base-displacement pairs the operand of the instruction (Agarwal discloses, at Figure 4 and related description, using the base-displacement pairs to retrieve operands that are used to execute the instructions.).
Regarding claim 9, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the single register is specified in instruction text of the instruction (Agarwal discloses, at Figure 4 and related description, the location designation is specified by the instruction text.).
Regarding claim 11, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the executing the instruction further includes obtaining one or more other operands of the instruction from one or more other operand locations specified by a configuration of the instruction (Agarwal discloses, at Figure 4 and related description, the instruction includes other operands specified by the instruction.).
Regarding claim 12, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the instruction is configured with a constraint limiting a number of operand locations to be specified by instruction text of the instruction… (Agarwal discloses, at Figure 4 and related description, the instruction specifies three operands.).
Agarwal does not explicitly disclose wherein using the single register to specify multiple designations of multiple operand locations increases the number of operand locations supported by the instruction.
However, in the same field of endeavor (e.g., processing instructions) Zaks discloses:
a single register that stores multiple addresses (Zaks discloses, at ¶ [0060] et seq., an operand field that designates a single vector register that stores multiple addresses. It is evident that the single register can specify more than the three or four operands the instruction word is limited to.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal to include storing the multiple base-displacement pairs, i.e., addresses, in a single register, as disclosed by Zaks, because referring to multiple operands using a single reference is a well-known aspect of parallel processing that allows increased performance due to more efficient programming.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Agarwal in view of Zaks in view of US Publication No. 2013/0339706 by Greiner et al. (hereinafter referred to as “Greiner”).
Regarding claim 10, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal does not explicitly disclose the single register is an implied register of the instruction.
However, in the same field of endeavor (e.g., processing instructions) Gainey discloses:
implied registers (Gainey discloses, at ¶ [0047], implied registers.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal to include implied registers, as disclosed by Gainey, in order to improve performance by allowing additional flexibility and capacity in defining instruction words.
Response to Arguments
On pages 12-18 of the response filed August 3, 2026 (“response”), the Applicant argues that Agarwal fails to disclose all elements of the amended claims.
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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