DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 9, 10, 13, 18, 23, and 24 have been amended.
Claims 1-25 have been examined.
The claim objections in the previous Office Action have been addressed and are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 5, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 11-25 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 5,832,533 by Agarwal et al. (hereinafter referred to as “Agarwal”).
Regarding claims 1, 13, 18, 23, and 24, taking claim 1 as representative, Agarwal discloses:
a computer program product comprising: a set of one or more computer-readable storage media; and program instructions, collectively stored in the set of one or more computer-readable storage media, for causing at least one computing device to perform computer operations including: executing an instruction within a computing environment, the instruction including an operand field, the operand field including a designation of a register, the register being a single register specified by the operand field of the instruction, the executing the instruction including: obtaining a plurality of operands of the instruction, the obtaining the plurality of operands including (Agarwal discloses, at Figure 1 and related description, a superscalar execution system including a vector processor, which discloses a computer program product comprising computer readable storage media storing instructions and causing a computing device to execute instructions including obtaining operands. Agarwal also discloses, at Figure 4 and related description, an operand field 320 that specifies a register.):
obtaining a plurality of operands of the instructions, the obtaining the plurality of operands comprising (Agarwal discloses, at Figure 4 and related description, instructions that involve obtaining multiple operands.):
retrieving from …the instruction …designations of …operand locations, the …operand locations used to provide … operands of the plurality of operands of the instruction (Agarwal discloses, at Figure 4 and related description, an instruction that specifies locations of the operands, which discloses retrieving form the instruction designations of operand locations that provide the operands.);
determining from the … operand locations the … operands of the instruction; (Agarwal discloses, at Figure 4 and related description, an instruction that specifies locations of the operands, which discloses determining the operand locations.) and
performing one or more operations of the instruction using one or more operands of the plurality of operands of the instruction to obtain a result of the instruction (Agarwal discloses, at Figure 4 and related description, an instruction that specifies an operation to perform and locations of the operands, which discloses performing operations of the instruction using operands of the instruction to obtain a result of the instruction.).
Agarwal does not explicitly disclose storing the operand location designations in a single register of the instruction and that the single register of the instruction includes multiple location designations for multiple operands.
However, Agarwal discloses, at Figure 4 and related description, an instruction that specifies a register, e.g., at element 322. Agarwal also discloses an instruction that includes specification of multiple locations, e.g., 304-308, in the instruction word itself. Finally, Agarwal also discloses, at Figure 3 and related description, vector registers that each store a plurality elements. It would have been obvious to modify Agarwal such that instead of storing the multiple operand locations in the instruction word itself, the multiple operand locations were stored in a single register specified by the instruction, e.g., specified in field 322. Doing so would allow specification of a greater number of operand locations than possible using the instruction word and would have enabled increased flexibility with regard to the use of bits in the instruction word.
Regarding claims 2, 14, and 19, taking claim 2 as representative, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the multiple designations of the multiple operand locations include multiple information sets, and wherein an information set of the multiple information sets includes a set of values that are combined and used to provide an operand of the multiple operands (Agarwal discloses, at Figure 4 and related description, combining the base and offset, which discloses an information set that includes values that are combined to provide an operand.).
Regarding claims 3, 15, and 20, taking claim 3 as representative, Agarwal, as modified, discloses the elements of claim 2, as discussed above. Agarwal also discloses:
the multiple information sets include multiple base-displacement pairs, the multiple base-displacement pairs used to determine the multiple operands of the instruction, and wherein the multiple base-displacement pairs are included in the register of the instruction (Agarwal discloses, at Figure 4 and related description, combining the base and offset, which discloses base-displacement pairs to determine the operands.).
Regarding claim 4, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the multiple designations of the multiple operand locations include multiple base-displacement pairs, the multiple base-displacement pairs used to determine the multiple operands of the instruction, and wherein the multiple base-displacement pairs are included in the register of the instruction (Agarwal discloses, at Figure 4 and related description, combining the base and offset, which discloses base-displacement pairs to determine the operands.).
Regarding claim 5, Agarwal, as modified, discloses the elements of claim 4, as discussed above. Agarwal also discloses:
a base-displacement pair provides a resulting value, the resulting value being an address indicating a location of an operand of the multiple operands (Agarwal discloses, at Figure 4 and related description, combining the base and offset to generate an address, which discloses base-displacement pairs to determine an address indicating a location of operands.).
Regarding claim 6, Agarwal, as modified, discloses the elements of claim 4, as discussed above. Agarwal also discloses:
a base-displacement pair of the multiple base-displacement pairs provides a resulting value, the resulting value being an operand of the multiple operands (Agarwal discloses, at Figure 4 and related description, combining the base and offset to generate an address, which discloses base-displacement pairs being an operand, e.g., in the case of a memory operation.).
Regarding claims 7, 16, and 21, taking claim 7 as representative, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the multiple designations of the multiple operand locations include multiple indications of multiple registers that include the multiple operands of the instruction, and wherein the multiple indications of the multiple registers are included in the register of the instruction (Agarwal discloses, at Figure 5 and related description, that the operand locations are registers.).
Regarding claims 8, 17, 22, and 25, taking claim 8 as representative, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the multiple designations of the multiple operand locations include at least one indication of at least one register that includes at least one operand of the instruction, and at least one base-displacement pair to be used to determine at least one other operand of the instruction (Agarwal discloses, at Figure 4 and related description, a direct address and a base/displacement pair, which discloses including an indication of at least one register and at least one base-displacement pair.).
Regarding claim 9, Agarwal, as modified, discloses the elements of claim 24, as discussed above. Agarwal also discloses:
the register is specified in instruction text of the instruction (Agarwal discloses, at Figure 4 and related description, the location designation is specified by the instruction text.).
Regarding claim 11, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the plurality of operands includes one or more other operands of the instruction, the one or more other operands of the instruction obtained from one or more other operand locations specified by a configuration of the instruction (Agarwal discloses, at Figure 4 and related description, the instruction includes other operands specified by the instruction.).
Regarding claim 12, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal also discloses:
the instruction is configured with a constraint limiting a number of the operand locations to be specified by instruction text of the instruction… (Agarwal discloses, at Figure 4 and related description, the instruction specifies three operands.).
Agarwal does not explicitly disclose wherein using the register to provide the multiple designations of the multiple operand locations increases the number of operand locations supported by the instruction
However Agarwal discloses, at Figure 3 and related description, vector registers that each store a plurality elements. It would have been obvious to pack the operand designations into the vector registers in order to provide efficient access to the designations, providing the ability to specify a larger number of operands with a single instruction, which is a fundamental benefit of vector processing.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Agarwal in view of US Publication No. 2013/0339706 by Greiner et al. (hereinafter referred to as “Greiner”).
Regarding claim 10, Agarwal, as modified, discloses the elements of claim 1, as discussed above. Agarwal does not explicitly disclose the register is an implied register of the instruction.
However, in the same field of endeavor (e.g., processing instructions) Gainey discloses:
implied registers (Gainey discloses, at ¶ [0047], implied registers.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal to include implied registers, as disclosed by Gainey, in order to improve performance by allowing additional flexibility and capacity in defining instruction words.
Response to Arguments
On page 10 of the response filed February 5, 2026 (“response”), the Applicant argues, “Applicant respectfully submits that one or more aspects of applicant's independent claim 1 is patentable over Agarwal. For instance, applicant respectfully submits that it appears that Agarwal fails to describe, teach or suggest, at least, one or more of applicant's claimed aspects of "the instruction including an operand field, the operand field including a designation of a register, the register being a single register specified by the operand field of the instruction, ... retrieving from the register of the instruction multiple designations of multiple operand locations, the register being the single register specified by the operand field of the instruction, and wherein the multiple operand locations provided by the single register are used to provide multiple operands of the plurality of operands of the instruction," as recited in, e.g., independent claim 1. While Agarwal mentions, "When an indexed addressing mode has been enabled, the operand field utilizing the index mode will contain a value having a format illustrated at operand 310. As illustrated, operand 310 includes indexed addressing bit 312, update bit 314, base register pointer field 316, and displacement field 318." (Col. 7, lines 16-21), applicant respectfully submits that this does not appear to be a description, teaching or suggestion of, for instance, applicant's claimed aspect of "the instruction including an operand field, the operand field including a designation of a register, the register being a single register specified by the operand field of the instruction, ... retrieving from the register of the instruction multiple designations of multiple operand locations, the register being the single register specified by the operand field of the instruction, and wherein the multiple operand locations provided by the single register are used to provide multiple operands of the plurality of operands of the instruction," as recited in, e.g., independent claim 1. There does not appear to be any discussion, teaching or suggestion in Agarwal of, for instance, "... the register being a single register specified by the operand field of the instruction, ... retrieving from the register of the instruction multiple designations of multiple operand locations, the register being the single register specified by the operand field of the instruction, and wherein the multiple operand locations provided by the single register are used to provide multiple operands of the plurality of operands of the instruction," as recited in, e.g., independent claim 1. For at least one or more of these reasons, applicant respectfully requests an indication of allowance for independent claim 1.”
Though fully considered, the Examiner respectfully disagrees. Agarwal discloses, at Figure 4 and related description, an instruction that includes an operand field that designates a register. For example, 320 is an operand field that designates a register. Agarwal also discloses an instruction including multiple designations of multiple operand locations. For example, fields 304-306 designate multiple operand locations.
The difference between the claims and Agarwal is that Agarwal does not explicitly discloses the multiple operand locations are included in a single register specified by the instruction. Instead, Agarwal discloses the multiple operand locations are specified in the instruction word itself. This is generally similar to immediate operands.
Whether to include information in the instruction word itself, e.g., as an immediate value, or in a register that is specified by the instruction is a decision based on well-known tradeoffs and is dictated by circumstances and design objectives. For example, storing data in the instruction word itself can facilitate relatively fast execution since a read to memory can be avoided. However, there are generally a limited number of bits in instruction words, and making instructions longer can be detrimental to performance by requiring longer fetch and decode cycles. Again, these considerations are well-known. Whether to store the multiple operand designations disclosed by Agarwal in the instruction word or in a register specified by the instruction word are obvious alternatives. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 11-12 of the response the Applicant argues the remaining claims are allowable for similar reasons.
Though fully considered, the Examiner respectfully disagrees. The remarks and rejections presented above apply similarly to these claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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