DETAILED ACTION
This action is responsive to the application filed July 31, 2024. Claims 1-20 are pending. Claims 1, 14, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims.
"each of the first memory cell and the second memory cell is configured to store two voltage levels that jointly represent one logical value" of claim 10.
"the first memory cell comprises: a first transistor coupled to a first capacitor; and a second transistor coupled to a second capacitor" of claim 11.
"the first memory cell is part of a first memory cell array; and the second memory cell is part of a second memory cell array" of claim 12.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claim 18 and claims 19-20, the phrase "a first/second memory array portion" (which are recited as connectable to the sense amplifier’s terminals by various switching devices) is a unclear term lacking reasonably ascertainable boundaries, which renders the claim indefinite. The “portion” is not defined by the claims and the specification does not provide a standard for ascertaining the boundaries of the physical region of the memory referenced that would or would not be a “portion” to thereby assist one of ordinary skill in the art to understand the scope of this claim.
Instead, from applicant’s originally filed disclosure and especially their drawings, the only “portion” illustrated as connected to the sense amplifier’s terminals through switching devices is the first memory cell (for BL1/BLB1) and the second memory cell (for BL2/BLB2). In this context, as would be understood from persons skilled in the memory art, the “portion” of the array can only be: any cell of the column that is connected to the sense amplifier. But, the definition of the term “portion” is not limiting, which is why the use of “portion” here renders the claim indefinite.
For purposes of compact prosecution (see MPEP 2173.06), the term “a first/second memory array portion” will be interpreted to mean "a first/second memory cell".
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 13-16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eaton et al. (US RE32682; "Eaton").
Regarding independent claim 1, Eaton discloses a memory device comprising:
a sense amplifier having a first terminal (Fig. 1:14 sense amplifier, with a first terminal near 10a for example);
a first bitline (Fig. 1:A bit line);
a first memory cell coupled to the first bitline (Fig. 1:M1 memory cell);
a second bitline (Fig. 1:C bit line);
a second memory cell coupled to the second bitline (Fig. 1:34 memory cell. See also col. 3, ln 41-42; "Similarly, memory cells groups 32, 34, and 36 are associated with bit lines B, C, and D, respectively");
a first switching device coupled between the first bitline and the first terminal of the sense amplifier (Fig. 1:10 isolation transistor. See also col. 2, ln 23-24; "The pair of bit lines A-B is coupled through isolation transistors 10 and 12 to a sense amplifier 14");
and a second switching device coupled between the second bitline and the first terminal of the sense amplifier (Fig. 1:16 isolation transistor. See also col. 2, ln 25-26; "The pair of bit lines C-D is similarly coupled to the sense amplifier 14 via isolation transistors 16 and 18").
Regarding claim 2, Eaton discloses the limitations of claim 1.
As applied, Eaton further discloses wherein:
the first switching device includes a first input coupled to the first bitline and a first output coupled to the first terminal of the sense amplifier (Fig. 1: 10 isolation transistor which connects the first terminal of the sense amplifier to bit line A of memory cell 30);
and the second switching device includes a second input coupled to the second bitline and a second output coupled to the first terminal of the sense amplifier (Fig. 1: 16 isolation transistor which connects the first terminal of the sense amplifier to bit line C of memory cell 34).
Regarding claim 3, Eaton discloses the limitations of claim 1.
As applied, Eaton further discloses wherein:
the first switching device is configured to selectively connect the first bitline to the first terminal of the sense amplifier based on a first selection signal (Fig. 1:60 select signal. See also col. 4, ln 33-34; "In order to select a pair of bit lines, a clock signal, indicated as ΦRPL, is generated and coupled via line 60 to the gates of the transistors 10");
and the second switching device is configured to selectively connect the second bitline to the first terminal of the sense amplifier based on a second selection signal (Fig.1:62 select signal. See also col. 4, ln. 35-37; " In addition, another clock signal, indicated as ΦRPR is generated and coupled via line 62 to the gates of the transistors 16").
Regarding claim 4, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses wherein:
a first control terminal of the first switching device is configured to receive the first selection signal (Fig. 1: 10 isolation transistor and it's gate (control terminal) is connected to receive selection signal ΦRPL);
and a second control terminal of the second switching device is configured to receive the second selection signal (Fig 1: 16 isolation transistor 16 and it's gate (control terminal) is connected to receive selection signal ΦRPR).
Regarding claim 5, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses wherein:
the first switching device is configured to connect the first bitline to the first terminal of the sense amplifier based on the first selection signal to enable the first memory cell to be read (Fig. 1 where it illustrates that memory cell 30 is enabled to be read by the sense amplifier when selection signal ΦRPL is active);
and the second switching device is configured to disconnect the second bitline from the first terminal of the sense amplifier based on the second selection signal to enable the first memory cell to be read (Fig. 1 where it illustrates that memory cell 30 is enabled to be read by the sense amplifier when selection signal ΦRPR is active).
Regarding claim 6, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses wherein:
the first switching device is configured to disconnect the first bitline from the first terminal of the sense amplifier based on the first selection signal during a time period (Fig. 1 where it illustrates that selection signal ΦRPL is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 10 (first switching device) is turned off during a time period, disconnecting the first bit line);
and the second switching device is configured to connect the second bitline to the first terminal of the sense amplifier based on the second selection signal during the time period (Fig. 1 where it illustrates that selection signal ΦRPR is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 16 (second switching device) is turned off during a time period, disconnecting the second bit line).
Regarding claim 7, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses further comprising:
a third bitline coupled to the first memory cell (Fig. 1: B bit line);
a third switching device coupled between the third bitline and a second terminal of the sense amplifier (Fig. 1: 12 isolation transistor which connects the second terminal of the sense amplifier to memory cell 32.);
a fourth bitline coupled to the second memory cell (Fig. 1: E bit line);
and a fourth switching device coupled between the fourth bitline and the second terminal of the sense amplifier (Fig. 1: 18 isolation transistor which connects the second terminal of the sense amplifier to memory cell 36.).
Regarding claim 8, Eaton discloses the limitations of claim 7.
As applied, Eaton further discloses wherein:
the third switching device includes a third input coupled to the third bitline and a third output coupled to the second terminal of the sense amplifier (Fig. 1: 12 isolation transistor which connects the first terminal of the sense amplifier to bit line B of memory cell 32);
and the fourth switching device includes a fourth input coupled to the fourth bitline and a fourth output coupled to the second terminal of the sense amplifier (Fig. 1: 18 isolation transistor which connects the first terminal of the sense amplifier to bit line D of memory cell 36).
Regarding independent claim 14, Eaton discloses a method performed by a memory device to share a sense amplifier between memory cells, the method comprising:
receiving, by a first switching device, a first selection signal (Fig. 1:60 select signal. See also col. 4, ln. 33-35; "In order to select a pair of bit lines, a clock signal, indicated as ΦRPL, is generated and coupled via line 60 to the gates of the transistors 10");
selectively connecting, by the first switching device, a first bitline to a first terminal of a sense amplifier based on the first selection signal, the first bitline coupled to a first memory cell (Fig 1 where it illustrates that transistor 10 connects bit line A to the first terminal of a sense amplifier 14 based on selection signal ΦRPL);
receiving, by a second switching device, a second selection signal (Fig.1:62 select signal. See also col. 4, ln 35-37; " In addition, another clock signal, indicated as ΦRPR is generated and coupled via line 62 to the gates of the transistors 16");
and selectively connecting, by the second switching device, a second bitline to the first terminal of the sense amplifier based on the second selection signal, the second bitline coupled to a second memory cell (Fig 1 where it illustrates that transistor 16 connects bit line C to the first terminal of sense amplifier 14 based on selection signal ΦRPR).
Regarding claim 15, Eaton discloses the limitations of claim 14.
As applied, Eaton further discloses further comprising:
connecting, by the first switching device, the first bitline to the first terminal of the sense amplifier based on the first selection signal during a first time period (Fig. 1 where it illustrates that selection signal ΦRPL is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is in the active state, isolation transistor 10 (first switching device) is turned on during a time period, connecting the first bit line);
and disconnecting, by the second switching device, the second bitline from the first terminal of the sense amplifier based on the second selection signal during the first time period (Fig. 1 where it illustrates that selection signal Φ is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 16 (second switching device) is turned off during a time period, disconnecting the second bit line).
Regarding claim 16, Eaton discloses the limitations of claim 15.
As applied, Eaton further discloses further comprising:
disconnecting, by the first switching device, the first bitline from the first terminal of the sense amplifier based on the first selection signal during a second time period (Fig. 1 where it illustrates that selection signal ΦRPL is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 10 (first switching device) is turned off during a second time period, disconnecting the first bit line);
and connecting, by the second switching device, the second bitline to the first terminal of the sense amplifier based on the second selection signal during the second time period (Fig. 1 where it illustrates that selection signal Φ is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is in the active state, isolation transistor 16 (second switching device) is turned on during a second time period, connecting the second bit line).
Regarding independent claim 18, notwithstanding the rejection for indefiniteness above, Eaton discloses an apparatus comprising:
a sense amplifier including a first terminal and a second terminal (Fig. 1 where it illustrates sense amplifier 14 with a first terminal near 10a and a second terminal near 12a);
a first switching device coupled between the first terminal and a first memory array portion (Fig. 1:10 isolation transistor which connects the first terminal of the sense amplifier to memory cell 30);
a second switching device coupled between the first terminal and a second memory array portion (Fig. 1: 16 isolation transistor which connects the first terminal of the sense amplifier to memory cell 34.);
a third switching device coupled between the second terminal and the first memory array portion (Fig. 1: 12 isolation transistor which connects the second terminal of the sense amplifier to memory cell 32.);
and a fourth switching device coupled between the second terminal and the second memory array portion (Fig. 1: 18 isolation transistor which connects the second terminal of the sense amplifier to memory cell 36.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Eaton et al. (US RE32682; "Eaton") in view of Watanabe et al. (US 5434821; "Watanabe")
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Regarding claim 9, Eaton discloses the limitations of claim 8.
While Eaton further discloses first through fourth switching devices and first through fourth bit lines coupled to the terminals of the sense amplifier, it is silent with respect to the specific combination of differential bit lines connecting to the terminals of the sense amplifier.
However, Watanabe teaches wherein:
the first switching device is configured to disconnect the first bitline from the first terminal of the sense amplifier based on the first selection signal during a time period (Fig. 21. First bit line is BL1. See also Examiner's markup above);
the second switching device is configured to connect the second bitline to the first terminal of the sense amplifier based on the second selection signal during the time period (Fig. 21);
the third switching device is configured to disconnect the third bitline from the second terminal of the sense amplifier based on the first selection signal during the time period (Fig. 21);
and the fourth switching device is configured to connect the fourth bitline to the second terminal of the sense amplifier based on the second selection signal during the time period (Fig. 21. Regarding the connecting of the second and fourth bit lines while disconnecting the first and third bit lines, see also Fig. 22 and col. 6, lns. 60-64; "In an active operation, one selected signal among the signals Φ1 through Φ4 is selected by an external selection circuit (not shown) and is set to "H" level and data from the selected bit lines is read out". It is noted that since only one selection signal is activated at a time, one pair of bit lines is necessarily connected while the other is disconnected).
Eaton and Watanabe are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Watanabe’s differential memory cells to halve the required number of sense amplifiers. Doing so would reduce the device floorplan area.
Regarding claim 17, Eaton discloses the limitations of claim 14.
While Eaton further discloses first through fourth switching devices and first through fourth bit lines coupled to the terminals of the sense amplifier, it is silent with respect to the specific combination of differential bit lines connecting to the terminals of the sense amplifier.
However, Watanabe teaches further comprising:
selectively connecting, by a third switching device, a third bitline to a second terminal of the sense amplifier based on the first selection signal, the third bitline coupled to the first memory cell (Fig. 21 where it illustrates the third switching device, on the third bitline /BL1, connected to the second terminal of the sense amplifier based on the first selection signal (see Examiner's Markup above));
and selectively connecting, by a fourth switching device, a fourth bitline to the second terminal of the sense amplifier based on the second selection signal, the fourth bitline coupled to the second memory cell (Fig. 21 where it illustrates the fourth switching device, on the fourth bitline /BL2, connected to the second terminal of the sense amplifier based on the second selection signal (see Examiner's Markup above). See also col. 6, ln. 69 - col. 7, ln. 1-2; "sense amplifier 70 could also be shared among two pairs of bit lines").
Eaton and Watanabe are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Watanabe’s differential memory cells to halve the required number of sense amplifiers. Doing so would reduce the device floorplan area.
Regarding claim 19, notwithstanding the rejection for indefiniteness above, Eaton discloses the limitations of claim 18.
While Eaton further discloses first through fourth switching devices and first through fourth bit lines coupled to the terminals of the sense amplifier, it is silent with respect to the specific combination of differential bit lines connecting to the terminals of the sense amplifier.
However, Watanabe teaches further comprising:
a controller configured to control the first switching device, the second switching device, the third switching device, and the fourth switching device to connect the first terminal and the second terminal to the first memory array portion and disconnect the first terminal and the second terminal from the second memory array portion during a first time period (Fig. 21 where it illustrates a plurality of differential DRAM cells sharing a differential sense amplifier (70). See also Fig. 22 and col. 6, lns 60-64; "In an active operation, one selected signal among the signals Φ1 through Φ4 is selected by an external selection circuit (not shown) and is set to "H" level and data from the selected bit lines is read out". It is noted that the external selection circuit is necessarily a controller.).
Eaton and Watanabe are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Watanabe’s differential memory cells to halve the required number of sense amplifiers. Doing so would reduce the device floorplan area.
Regarding claim 20, notwithstanding the rejection for indefiniteness above, Eaton and Watanabe disclose the limitations of claim 19.
As applied, Watanabe further discloses wherein:
the controller is further configured to control the first switching device, the second switching device, the third switching device, and the fourth switching device to disconnect the first terminal and the second terminal from the first memory array portion and connect the first terminal and the second terminal to the second memory array portion during a second time period, the first time period different from the second time period (Fig. 21 where it illustrates a plurality of differential DRAM cells sharing a differential sense amplifier (70). See also Fig. 22 and col. 6, lns. 60-64; "In an active operation, one selected signal among the signals Φ1 through Φ4 is selected by an external selection circuit (not shown) and is set to "H" level and data from the selected bit lines is read out". It is noted that the external selection circuit is necessarily a controller.).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Eaton et al. (US RE32682; "Eaton") in view of Liu (US 9478277).
Regarding claim 10, Eaton discloses the limitations of claim 7.
As applied, Eaton further discloses wherein:
the sense amplifier comprises a differential sense amplifier (Fig. 1: 14 differential sense amplifier. See also col. 3, ln. 55-57; "The sense amplifier 20 operates in the same manner as the sense amplifier 14 to sense the voltage differential between bit lines");
Eaton is silent with respect to the memory cell storing more than one voltage level.
However, Liu teaches and each of the first memory cell and the second memory cell is configured to store two voltage levels that jointly represent one logical value (Fig. 1 where it illustrates TLC dram memory cells with a shared differential sense amplifier. See also abst: "Tri-level-cell dynamic random access memory (DRAM) stores 3 levels of voltage (0, VDD/2, VDD) into a plurality of memory cells.").
Eaton and Liu are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Liu’s multi-level memory cells to increase the storage density of the memory array. Doing so would reduce the device floorplan area.
Regarding claim 12, Eaton discloses the limitations of claim 1.
Eaton is silent with respect to the specific array containing the memory cells.
However, Liu teaches wherein:
the first memory cell is part of a first memory cell array; and the second memory cell is part of a second memory cell array (Fig. 5 where it illustrates bit lines from multiple memory arrays connecting to shared sense amplifiers (SA)).
Eaton and Liu are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Liu’s memory cells in different arrays. Doing so would allow greater design flexibility with respect to device layout.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Eaton et al. (US RE32682; "Eaton") in view of Foss et al. (US 5414662; "Foss").
Regarding claim 11, Eaton discloses the limitations 11 of claim 1.
While Eaton discloses the use of DRAM memory cells, it is silent with respect to the memory cell having more than one transistor and capacitor.
However, Foss teaches wherein the first memory cell comprises:
a first transistor coupled to a first capacitor; and a second transistor coupled to a second capacitor (Fig. 1 where it illustrates a differential DRAM memory cell with first capacitor 5A and second capacitor 5B).
Eaton and Foss are from the same field of endeavor as applicant’s invention directed to DRAM memory cells coupled to a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Foss’s differential logic memory cells. Doing so would improve data integrity, reliability, and noise margin.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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