DETAILED ACTION
This action is responsive to the amendments filed July 7, 2026. Claims 1-20 are pending. Claims 1, 13, 14 and 18 have been amended. Claims 1, 14, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant’s amendments to the specification to support the drawing amendments are acknowledged and accepted.
Drawings
Applicant’s amendments to the drawings is acknowledged and accepted. The objection to the drawings has been withdrawn.
Response to Amendment
Applicant’s arguments with respect to the indefiniteness rejection regarding the phrase “a first/second memory array portion" are persuasive. The 35 USC § 112(b) rejection for claims 18-20 have been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 13-16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eaton et al. (US RE32682; "Eaton" – of record).
Regarding independent claim 1, Eaton discloses a memory device comprising:
a sense amplifier having a first terminal (Fig. 1:14 sense amplifier. See also col. 3, ln. 14-16; “ terminal 10a of the transistor 10 is coupled to the drain of the transistor 22 and to the gate of the transistor 24.”)
a first bitline (Fig. 1:A bit line);
a first memory cell coupled to the first bitline (Fig. 1:M1 memory cell);
a second bitline (Fig. 1:C bit line);
a second memory cell coupled to the second bitline (Fig. 1. See also col. 3, ln 41-42; "Similarly, memory cells groups 32, 34, and 36 are associated with bit lines B, C, and D, respectively");
a first switching device coupled between the first bitline and the first terminal of the sense amplifier (Fig. 1:10 isolation transistor. See also col. 2, ln 23-24; "The pair of bit lines A-B is coupled through isolation transistors 10 and 12 to a sense amplifier 14");
and a second switching device coupled between the second bitline and the first terminal of the sense amplifier (Fig. 1:16 isolation transistor. See also col. 2, ln 25-26; "The pair of bit lines C-D is similarly coupled to the sense amplifier 14 via isolation transistors 16 and 18"),
the first memory cell and the second memory cell comprising memory cells configured to store usage-based-disturbance (UBD) data (col. 1, ln. 16-18; “Each cell includes a capacitor for storing a charge which indicates whether its cell is in a logic 1 or a logic 0 state.”. It is noted that the newly added limitation of the memory cells being configured to store usage-based-disturbance (UBD) data does not recite any functional relationship between the stored bit and the rest of the apparatus (no count update, no compare, no refresh, no UBD circuit. It is nothing more than a label for the data (information content) stored in Eaton’s DRAM cells. Under MPEP 2111.05(I)(A), to be given patentable weight, the printed matter (information content) and the associated product must be in a functional relationship. A functional relationship can be found where the printed matter (information content) performs some function with respect to the product to which it is associated. UBD data is non-functional descriptive matter characterizing what the already claimed cells are intended to hold. Eaton’s cells remain cells configured to store data and therefore claim 1 is anticipated.
Regarding claim 2, Eaton discloses the limitations of claim 1.
As applied, Eaton further discloses wherein:
the first switching device includes a first input coupled to the first bitline and a first output coupled to the first terminal of the sense amplifier (Fig. 1: 10 isolation transistor which connects the first terminal of the sense amplifier to bit line A of memory cell 30);
and the second switching device includes a second input coupled to the second bitline and a second output coupled to the first terminal of the sense amplifier (Fig. 1: 16 isolation transistor which connects the first terminal of the sense amplifier to bit line C of memory cell 34).
Regarding claim 3, Eaton discloses the limitations of claim 1.
As applied, Eaton further discloses wherein:
the first switching device is configured to selectively connect the first bitline to the first terminal of the sense amplifier based on a first selection signal (Fig. 1:60 select signal. See also col. 4, ln 33-34; "In order to select a pair of bit lines, a clock signal, indicated as ΦRPL, is generated and coupled via line 60 to the gates of the transistors 10");
and the second switching device is configured to selectively connect the second bitline to the first terminal of the sense amplifier based on a second selection signal (Fig.1:62 select signal. See also col. 4, ln. 35-37; " In addition, another clock signal, indicated as ΦRPR is generated and coupled via line 62 to the gates of the transistors 16").
Regarding claim 4, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses wherein:
a first control terminal of the first switching device is configured to receive the first selection signal (Fig. 1: 10 isolation transistor and it's gate (control terminal) is connected to receive selection signal ΦRPL);
and a second control terminal of the second switching device is configured to receive the second selection signal (Fig 1: 16 isolation transistor 16 and it's gate (control terminal) is connected to receive selection signal ΦRPR).
Regarding claim 5, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses wherein:
the first switching device is configured to connect the first bitline to the first terminal of the sense amplifier based on the first selection signal to enable the first memory cell to be read (Fig. 1 where it illustrates that memory cell 30 is enabled to be read by the sense amplifier when selection signal ΦRPL is active);
and the second switching device is configured to disconnect the second bitline from the first terminal of the sense amplifier based on the second selection signal to enable the first memory cell to be read (Fig. 1 where it illustrates that memory cell 30 is enabled to be read by the sense amplifier when selection signal ΦRPR is active).
Regarding claim 6, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses wherein:
the first switching device is configured to disconnect the first bitline from the first terminal of the sense amplifier based on the first selection signal during a time period (Fig. 1 where it illustrates that selection signal ΦRPL is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 10 (first switching device) is turned off during a time period, disconnecting the first bit line);
and the second switching device is configured to connect the second bitline to the first terminal of the sense amplifier based on the second selection signal during the time period (Fig. 1 where it illustrates that selection signal ΦRPR is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 16 (second switching device) is turned off during a time period, disconnecting the second bit line).
Regarding claim 7, Eaton discloses the limitations of claim 3.
As applied, Eaton further discloses further comprising:
a third bitline coupled to the first memory cell (Fig. 1: B bit line);
a third switching device coupled between the third bitline and a second terminal of the sense amplifier (Fig. 1: 12 isolation transistor which connects the second terminal of the sense amplifier to memory cell 32.);
a fourth bitline coupled to the second memory cell (Fig. 1: E bit line);
and a fourth switching device coupled between the fourth bitline and the second terminal of the sense amplifier (Fig. 1: 18 isolation transistor which connects the second terminal of the sense amplifier to memory cell 36.).
Regarding claim 8, Eaton discloses the limitations of claim 7.
As applied, Eaton further discloses wherein:
the third switching device includes a third input coupled to the third bitline and a third output coupled to the second terminal of the sense amplifier (Fig. 1: 12 isolation transistor which connects the first terminal of the sense amplifier to bit line B of memory cell 32);
and the fourth switching device includes a fourth input coupled to the fourth bitline and a fourth output coupled to the second terminal of the sense amplifier (Fig. 1: 18 isolation transistor which connects the first terminal of the sense amplifier to bit line D of memory cell 36).
Regarding claim 13, Eaton discloses the limitations of claim 1.
As applied, Eaton further discloses wherein the usage-based-disturbance (UBD) data comprises at least one logical value that forms at least part of an activation count (col. 3, ln. 34-35; “This capacitor conventionally stores a charge which is indicative of the logic state of the cell M1.”. See also col. 1, ln. 16-18; “Each cell includes a capacitor for storing a charge which indicates whether its cell is in a logic 1 or a logic 0 state.”. It is noted that activation count is a further label on that bit. See MPEP 2111.05. Eaton’s cell stores a logical value. What applicant calls that value does not distinguish from the prior art.
Regarding independent claim 14, Eaton discloses a method performed by a memory device to share a sense amplifier between memory cells, the method comprising:
receiving, by a first switching device, a first selection signal (Fig. 1:60 select signal. See also col. 4, ln. 33-35; "In order to select a pair of bit lines, a clock signal, indicated as ΦRPL, is generated and coupled via line 60 to the gates of the transistors 10");
selectively connecting, by the first switching device, a first bitline to a first terminal of a sense amplifier based on the first selection signal, the first bitline coupled to a first memory cell that is configured to store usage-based-disturbance (UBD) data (Fig 1 where it illustrates that transistor 10 connects bit line A to the first terminal of a sense amplifier 14 based on selection signal ΦRPL. Regarding the newly amended UBD data, as noted in the rejection for claim 1 above, the label UBD data is non-functional descriptive matter characterizing what the already claimed cells are intended to hold and therefore has no patentable weight. Eaton’s cells remain cells configured to store data.);
receiving, by a second switching device, a second selection signal (Fig.1:62 select signal. See also col. 4, ln 35-37; " In addition, another clock signal, indicated as ΦRPR is generated and coupled via line 62 to the gates of the transistors 16");
and selectively connecting, by the second switching device, a second bitline to the first terminal of the sense amplifier based on the second selection signal, the second bitline coupled to a second memory cell that is configured to store usage-based-disturbance (UBD) data.(Fig 1 where it illustrates that transistor 16 connects bit line C to the first terminal of sense amplifier 14 based on selection signal ΦRPR. Regarding the newly amended UBD data, as noted in the rejection for claim 1 above, the label UBD data is non-functional descriptive matter characterizing what the already claimed cells are intended to hold and therefore has no patentable weight. Eaton’s cells remain cells configured to store data.);
Regarding claim 15, Eaton discloses the limitations of claim 14.
As applied, Eaton further discloses further comprising:
connecting, by the first switching device, the first bitline to the first terminal of the sense amplifier based on the first selection signal during a first time period (Fig. 1 where it illustrates that selection signal ΦRPL is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is in the active state, isolation transistor 10 (first switching device) is turned on during a time period, connecting the first bit line);
and disconnecting, by the second switching device, the second bitline from the first terminal of the sense amplifier based on the second selection signal during the first time period (Fig. 1 where it illustrates that selection signal Φ is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 16 (second switching device) is turned off during a time period, disconnecting the second bit line).
Regarding claim 16, Eaton discloses the limitations of claim 15.
As applied, Eaton further discloses further comprising:
disconnecting, by the first switching device, the first bitline from the first terminal of the sense amplifier based on the first selection signal during a second time period (Fig. 1 where it illustrates that selection signal ΦRPL is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is not in the active state, isolation transistor 10 (first switching device) is turned off during a second time period, disconnecting the first bit line);
and connecting, by the second switching device, the second bitline to the first terminal of the sense amplifier based on the second selection signal during the second time period (Fig. 1 where it illustrates that selection signal Φ is driven based on clock signal ΦL which oscillates as illustrated in Fig. 3. Thus, when the selection signal is in the active state, isolation transistor 16 (second switching device) is turned on during a second time period, connecting the second bit line).
Regarding independent claim 18, Eaton discloses an apparatus comprising:
a sense amplifier including a first terminal and a second terminal (Fig. 1. See also col. 3, ln. 11-18; “the sense amplifier 14, this device includes transistors 22 and 24 which are interconnected as a flip-flop with voltage nodes 21 and 23. As shown, terminal 10a of the transistor 10 is coupled to the drain of the transistor 22 and to the gate of the transistor 24. Terminal 12a of the transistor 12 is coupled to the drain of the transistor 24 and to the gate of the transistor 22.”;
a first switching device coupled between the first terminal and a first memory array portion comprising a first memory cell (col. 3, ln. 31-44; “An exemplary memory cell M1 is shown coupled to bit line A for accessing. Memory cell M1 includes a transistor 26 and a memory cell capacitor Cm. This capacitor conventionally stores a charge which is indicative of the logic state of the cell M1… Additional memory cells 30, each similar to the cell M1, are also associated with bit line… Similarly, memory cells groups 32, 34, and 36 are associated with bit lines B, C, and D, respectively,”)
that is configured to store usage-based- disturbance (UBD) data; (col. 3, ln. 16-18; “Each cell includes a capacitor for storing a charge which indicates whether its cell is in a logic 1 or a logic 0 state. As noted in the rejection for claim 1 above, no UBD circuit, no count update, no compare and no refresh are cited. The contents label is non-functional descriptive matter / intended use (MPEP 2111.05). Eaton’s cell is configured to store a bit.)
a second switching device coupled between the first terminal and a second memory array portion
(Fig. 1. See also col. 2, ln. 25-27; “The pair of bit lines C-D is similarly coupled to the sense amplifier 14 via isolation transistors 16 and 18.” See also col. 3, ln. 22-24; “As shown, terminal 16a of the transistor 16 is coupled to the drain of transistor 22 and to the gate of transistor 24.” Further see col. 3, ln. 42-46; “Similarly, memory cells groups 32, 34, and 36 are associated with bit lines B, C, and D, respectively, and may be selectively coupled to their associated bit lines when addressed by their own word lines.”
comprising a second memory cell that is configured to store usage-based-disturbance (UBD) data (col. 3, ln. 16-18; “Each cell includes a capacitor for storing a charge which indicates whether its cell is in a logic 1 or a logic 0 state. As noted above, no UBD circuit, no count update, no compare and no refresh are cited. The contents label is non-functional descriptive matter / intended use (MPEP 2111.05). Eaton’s cell is configured to store a bit.);
a third switching device coupled between the second terminal and the first memory array portion (Fig. 1: 12 isolation transistor which connects the second terminal of the sense amplifier to memory cell 32.);
and a fourth switching device coupled between the second terminal and the second memory array portion (Fig. 1: 18 isolation transistor which connects the second terminal of the sense amplifier to memory cell 36.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Eaton et al. (US RE32682; "Eaton"- of record) in view of Watanabe et al. (US 5434821; "Watanabe" – of record)
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Regarding claim 9, Eaton discloses the limitations of claim 8.
While Eaton further discloses first through fourth switching devices and first through fourth bit lines coupled to the terminals of the sense amplifier, it is silent with respect to the specific combination of differential bit lines connecting to the terminals of the sense amplifier.
However, Watanabe teaches wherein:
the first switching device is configured to disconnect the first bitline from the first terminal of the sense amplifier based on the first selection signal during a time period (Fig. 21. First bit line is BL1. See also Examiner's markup above);
the second switching device is configured to connect the second bitline to the first terminal of the sense amplifier based on the second selection signal during the time period (Fig. 21);
the third switching device is configured to disconnect the third bitline from the second terminal of the sense amplifier based on the first selection signal during the time period (Fig. 21);
and the fourth switching device is configured to connect the fourth bitline to the second terminal of the sense amplifier based on the second selection signal during the time period (Fig. 21. Regarding the connecting of the second and fourth bit lines while disconnecting the first and third bit lines, see also Fig. 22 and col. 6, lns. 60-64; "In an active operation, one selected signal among the signals Φ1 through Φ4 is selected by an external selection circuit (not shown) and is set to "H" level and data from the selected bit lines is read out". It is noted that since only one selection signal is activated at a time, one pair of bit lines is necessarily connected while the other is disconnected).
Eaton and Watanabe are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Watanabe’s differential memory cells to halve the required number of sense amplifiers. Doing so would reduce the device floorplan area.
Regarding claim 17, Eaton discloses the limitations of claim 14.
While Eaton further discloses first through fourth switching devices and first through fourth bit lines coupled to the terminals of the sense amplifier, it is silent with respect to the specific combination of differential bit lines connecting to the terminals of the sense amplifier.
However, Watanabe teaches further comprising:
selectively connecting, by a third switching device, a third bitline to a second terminal of the sense amplifier based on the first selection signal, the third bitline coupled to the first memory cell (Fig. 21 where it illustrates the third switching device, on the third bitline /BL1, connected to the second terminal of the sense amplifier based on the first selection signal (see Examiner's Markup above));
and selectively connecting, by a fourth switching device, a fourth bitline to the second terminal of the sense amplifier based on the second selection signal, the fourth bitline coupled to the second memory cell (Fig. 21 where it illustrates the fourth switching device, on the fourth bitline /BL2, connected to the second terminal of the sense amplifier based on the second selection signal (see Examiner's Markup above). See also col. 6, ln. 69 - col. 7, ln. 1-2; "sense amplifier 70 could also be shared among two pairs of bit lines").
Eaton and Watanabe are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Watanabe’s differential memory cells to halve the required number of sense amplifiers. Doing so would reduce the device floorplan area.
Regarding claim 19, Eaton discloses the limitations of claim 18.
While Eaton further discloses first through fourth switching devices and first through fourth bit lines coupled to the terminals of the sense amplifier, it is silent with respect to the specific combination of differential bit lines connecting to the terminals of the sense amplifier.
However, Watanabe teaches further comprising:
a controller configured to control the first switching device, the second switching device, the third switching device, and the fourth switching device to connect the first terminal and the second terminal to the first memory array portion and disconnect the first terminal and the second terminal from the second memory array portion during a first time period (Fig. 21 where it illustrates a plurality of differential DRAM cells sharing a differential sense amplifier (70). See also Fig. 22 and col. 6, lns 60-64; "In an active operation, one selected signal among the signals Φ1 through Φ4 is selected by an external selection circuit (not shown) and is set to "H" level and data from the selected bit lines is read out". It is noted that the external selection circuit is necessarily a controller.).
Eaton and Watanabe are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Watanabe’s differential memory cells to halve the required number of sense amplifiers. Doing so would reduce the device floorplan area.
Regarding claim 20, Eaton and Watanabe disclose the limitations of claim 19.
As applied, Watanabe further discloses wherein:
the controller is further configured to control the first switching device, the second switching device, the third switching device, and the fourth switching device to disconnect the first terminal and the second terminal from the first memory array portion and connect the first terminal and the second terminal to the second memory array portion during a second time period, the first time period different from the second time period (Fig. 21 where it illustrates a plurality of differential DRAM cells sharing a differential sense amplifier (70). See also Fig. 22 and col. 6, lns. 60-64; "In an active operation, one selected signal among the signals Φ1 through Φ4 is selected by an external selection circuit (not shown) and is set to "H" level and data from the selected bit lines is read out". It is noted that the external selection circuit is necessarily a controller.).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Eaton et al. (US RE32682; "Eaton" – of record) in view of Liu (US 9478277 – of record).
Regarding claim 10, Eaton discloses the limitations of claim 7.
As applied, Eaton further discloses wherein:
the sense amplifier comprises a differential sense amplifier (Fig. 1: 14 differential sense amplifier. See also col. 3, ln. 55-57; "The sense amplifier 20 operates in the same manner as the sense amplifier 14 to sense the voltage differential between bit lines");
Eaton is silent with respect to the memory cell storing more than one voltage level.
However, Liu teaches and each of the first memory cell and the second memory cell is configured to store two voltage levels that jointly represent one logical value (Fig. 1 where it illustrates TLC dram memory cells with a shared differential sense amplifier. See also abst: "Tri-level-cell dynamic random access memory (DRAM) stores 3 levels of voltage (0, VDD/2, VDD) into a plurality of memory cells.").
Eaton and Liu are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Liu’s multi-level memory cells to increase the storage density of the memory array. Doing so would reduce the device floorplan area.
Regarding claim 12, Eaton discloses the limitations of claim 1.
Eaton is silent with respect to the specific array containing the memory cells.
However, Liu teaches wherein:
the first memory cell is part of a first memory cell array; and the second memory cell is part of a second memory cell array (Fig. 5 where it illustrates bit lines from multiple memory arrays connecting to shared sense amplifiers (SA)).
Eaton and Liu are from the same field of endeavor as applicant’s invention directed to memory cells sharing a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Liu’s memory cells in different arrays. Doing so would allow greater design flexibility with respect to device layout.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Eaton et al. (US RE32682; "Eaton" – of record) in view of Foss et al. (US 5414662; "Foss" – of record).
Regarding claim 11, Eaton discloses the limitations 11 of claim 1.
While Eaton discloses the use of DRAM memory cells, it is silent with respect to the memory cell having more than one transistor and capacitor.
However, Foss teaches wherein the first memory cell comprises:
a first transistor coupled to a first capacitor; and a second transistor coupled to a second capacitor (Fig. 1 where it illustrates a differential DRAM memory cell with first capacitor 5A and second capacitor 5B).
Eaton and Foss are from the same field of endeavor as applicant’s invention directed to DRAM memory cells coupled to a sense amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eaton’s differential shared sense amplifier with the teachings of Foss’s differential logic memory cells. Doing so would improve data integrity, reliability, and noise margin.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant contends on pg. 23 of Remarks that the anticipation rejection for independent claims 1, 14 and 18 are improper because Eaton does not teach a newly amended feature of the claim.
Applicant does not contest that Eaton discloses a sense amplifier shared between memory cells through isolation transistors on the bit lines. The only argument on the merits is that Eaton “neither describes nor suggests anything related to storing ‘usage-based-disturbance (UBD) data,’” and that amending independent claims 1, 14, and 18 to include the language of original claim 13 therefore distinguishes those claims from Eaton, alone or in combination.
Amended claim 1 recites that “the first memory cell and the second memory cell comprising memory cells configured to store usage-based-disturbance (UBD) data.” Amended claim 14 recites that each of the first and second memory cells “is configured to store usage-based-disturbance (UBD) data.” Amended claim 18 recites that each memory array portion comprises a memory cell “configured to store usage-based-disturbance (UBD) data.” Amended claim 13 further recites that the UBD data “comprises at least one logical value that forms at least part of an activation count.”
None of those claims recites a usage-based-disturbance mitigation circuit, an increment or other update of the stored value, a comparison of the stored value to a threshold, or a refresh of a victim row. Those operations are described in the specification (paras. 21-22, 28, 36-38), but they are not claimed.
Eaton discloses DRAM memory cells that store a logic 1 or a logic 0 on a capacitor. Under MPEP 2114(II) covering intended use, apparatus claims cover what a device is, not what a device does. “Configured to store UBD data” does not require circuit 120. Additionally, under MPEP 2111.05, printed matter and other informational content that is not functionally related to the substrate cannot distinguish a claim from the prior art. The phrases “usage-based-disturbance (UBD) data” and “activation count” characterize what the already-claimed memory cells are intended to hold. They do not change the sense amplifier, the bit lines, the memory cells, or the isolation transistors. Applicant is correct that Eaton does not use the words “usage-based-disturbance” or “activation count.” That is not the test. The test is whether the claim, given its broadest reasonable interpretation, reads on Eaton. A memory cell configured to store a logic value reads on cell M1 and on a cell of group 34.
For at least these reasons, the rejection of independent claims 1, 14, and 18 are maintained. Claims 2–13, 15–17, 19, and 20 depend from the independent claims and therefore also remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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