DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11671084 and claims 1-20 of U.S. Patent No. 12101091. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent’s claims and application’s claims recite similar limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Robins et al. (US 20170330874) in view of Tobita et al. (US 5544102) and Lee et al (US 8107290).
As to claim 1, Robins et al.’s figure 7A shows a circuit comprising first and second capacitors 721 and 741. The figure fails to show that the capacitors are MOSFETs. However, Tobita et al.’s figures 3-4C shows that capacitors are formed with MOSFETs. Therefore, it would have been obvious to one having ordinary skill in the art to use MOSFETs, with one of the layouts shown in Tobita et al.’s figures, for Robins et al.’s first and second capacitors for the purpose of saving space. Therefore, the modified Robin et al.’s figure 7A shows an integrated circuit comprising: a first transistor (the modified 731 with one of Tobita’s transistors) and a second transistor on a substrate (see Tobita’s figures 6-18); a first conducting line (VDD’) in a first metal layer and connecting a gate of the first transistor, the first conducting line is configured to receive a first supply voltage for a lower voltage domain; a second conducting line (GND’ or GND) in the first metal layer and connecting a gate of the second transistor, where the second conducting line configured to receive an alternative supply voltage, wherein the first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor; a third conducting line (VDD) connected to a source and a drain of the first transistor and configured to receive a first reference voltage for a higher voltage domain; and a fourth conducting line connected to a source and a drain of the second transistor and configured to receive a second reference voltage for the higher voltage domain. The modified Robins et al.’s figure fails to show the structure of capacitor 706. However, Lee et al.’s figure 6 shows MIM capacitor 260 is connected between two MOS capacitors 250 and 130. Therefore, it would have been obvious to one having ordinary skill in the art to use MIM capacitor for Robins et al.’s capacitor 260 for the purpose of reducing coupling ratio and capacitor size. Thus, the modified Robins et al.’s figure further shows that the first conductive line and the second conducting line form a metal-insulator-metal capacitor connected between the gate of the first transistor and the gate second transistor (Lee et al.’s figure 7 shows that capacitor 260 comprises top and bottom metal layers respectively connected to the gates of the MOS capacitors. Therefore, the top and bottom metal layers of the modified Robins et al.’s capacitor 706 together with the gates of the MOS capacitors 941 and 951 form first and second conducting lines).
As to claim 2, the modified Robins et al.’s figure 7A shows a first active-region structure and a second active-region structure on the substrate; wherein the first transistor has a first gate-conductor intersecting the first active-region structure at a channel region of the first transistor; and the second transistor has a second gate-conductor intersecting the second active-region structure at a channel region of the second transistor (see Tobita;s figures 6-18).
As to claim 3, the modified Robins et al.’s figure 7A shows that the first gate conductor connected to the first conducting line through a first via-connector; and the second gate-conductor is connected to the second conducting line through a second via-connector.
As to claim 4, the modified Robins et al.’s figure 7A shows a first terminal-conductor and a second terminal-conductor intersecting the first active-region structure correspondingly at a source region and a drain region of the first transistor, and each of the first terminal-conductor and the second terminal-conductor is connected to the third conducting line through a corresponding via-connector; and a third terminal-conductor and a fourth terminal-conductor intersecting the second active-region structure correspondingly at a source region and a drain region of the second transistor, and each of the third terminal-conductor and the fourth terminal-conductor is connected to the fourth conducting line through a corresponding via-connector (Tobita’s figures 6-18).
Claims 5-8 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
As to claim 9, Tobita’s figure 4A shows that both of the capacitors are PMOS transistors. Selecting the transistors as claimed for Robins et al.’s capacitors is seen as an obvious design preference to ensure optimum performance.
As to claims 10-15 and 17, Robins et al.’s 7A further shows a plurality of logic cells (720 and 710) in a lower voltage domain between the first power rail and the second power rail.
As to claim 16, it would have been obvious to one having ordinary skill in the art to use the first power supply rail to provide power to a level shifter for the purpose of achieving desired signal amplitude.
As to claim 18, Tobita et al.’s figure 4b and 4c shows that its first and second capacitors are formed with PMOS transistor and NMOS transistor. Selecting the transistors as claimed for Robin et al.’s capacitors is seen as an obvious design preference to ensure optimum performance.
As to claim 19, Tobita et al.’s figure 3a shows that its first and second capacitors are formed with NMOS transistors. Selecting the transistors as claimed for Robin et al.’s capacitors is seen as an obvious design preference to ensure optimum performance.
As to claim 20, Tobita et al.’s figure 4A shows that its first and second capacitors are formed with PMOS transistors. Selecting the transistors as claimed for Robin et al.’s capacitors is seen as an obvious design preference to ensure optimum performance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M.
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/QUAN TRA/
Primary Examiner
Art Unit 2842