3Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-9 of the remarks, filed 3/20/2026, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hida (US 2012/0159051).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-12, 14-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj (US 2109/01369899) in view of Hida (US 2012/0159051, as listed on the IDS dated 3/20/2026).
In regards to claims 1, 8, and 15, taking claim 1 as exemplary Tanpairoj teaches
a memory device comprising a cache and a primary storage band; (¶59-60 teaches a memory device can have SLC cells that are used as a cache and the data is later transferred to MLC memory cells (i.e. primary storage band)
and a processing device, operatively coupled with memory device, to perform operations comprising: (fig. 1, ¶26 memory device 110 contains a memory controller 115 (processing device)
detecting an occurrence of a rate control trigger event; (¶63-64 teaches that operational parameters are collected and evaluated based on one or more initiation rules to determine if they meet conditions to start, adjust, or terminate the migration process (i.e. if a condition has been met, then “an occurrence of a rate control trigger” has been detected)
collecting one or more operating statistics of the system at a time of the rate control trigger event, wherein the one or more operating statistics comprise an amount of free space in the cache of the memory device; (¶63-66 teaches that operational parameters are collected and evaluated based on one or more initiation rules to determine if they meet conditions to start, adjust, or terminate the migration process. Operational parameters are one or more measurements of a current operational state of the NAND device. The amount of free space in the cache is used as a condition for determining to migrate data. As the parameters are used to determine if a trigger has been met, then they were being collected and evaluated at the time the “rate control trigger event”)
determining, based on the one or more operating statistics, a target rate for migrating data from the cache to the primary storage band of the memory device; (¶64 teaches that rules of the MLC migration profile evaluate the operational parameters and determine how fast to perform the migration (i.e. determine a target rate)
Tanpairoj may not explicitly teach
Determining…an operating gear of a host system;
wherein determining the operating gear comprises comparing the amount of free space in the cache to respective threshold levels of free space corresponding to each of a plurality of operating gears;
configuring one or more data rate control parameters of the system based on the target rate for migrating data from the cache to the primary storage band of the memory device.
However, Hida teaches in ¶128-145 and fig. 17-20 that an operating mode (i.e. gear) is determined based upon the amount of free space in the cache, with multiple modes (i.e. gears) corresponding to an amount of free space in the cache, and that a transmission rate (i.e. data rate control parameters) can then be set based on those factors.
Tapiaroj also clearly suggests in ¶63-64 that the speed of migration can be controlled based off of migration parameter rules and fig. 7 and ¶74 gives an example of how clock speed can be throttled to control the rate of migration.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to incorporate the teachings of Hida, such that the operational mode (i.e. gears) could be determined and taken into account along with other operation parameters (as taught by Tapiaroj) when modifying the migration rate and/or throttling the data rate from the host. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been able to make these modifications and been able to achieve predictable results, and the motivation for making such a combination is that by properly controlling/throttling the rate at which data is received by the cache and migrated out of the cache the system can be better optimized for throughput and/or power savings.
In regards to claims 2 and 9, Tanpairoj further teaches and/or makes obvious
wherein the cache of the memory device comprises single-level-cell (SLC) memory, and wherein the primary storage band of the memory device comprises quad-level-cell (QLC) memory. (¶59-60 teaches a memory device can have SLC cells that are used as a cache and the data is later transferred to MLC memory cells (i.e. primary storage band) and that the MLC may refer to QLC.
In regards to claims 3, 10, and 16 Tanpairoj further teaches and/or makes obvious
wherein detecting the occurrence of the rate control trigger event comprises detecting at least one of selection of a new segment for folding data within the primary storage band of the memory device or selection of a new destination in the primary storage band for storing the data migrated from the cache of the memory device. (¶66 teaches that condition for initiating the migration process (rate control trigger) can be the amount of free space of the MLC dropping below a threshold. As the amount of free space (i.e. blocks/pages) drops, this is an indication that data is going to have to be stored and/or folded into MLC into previously unused areas (i.e. new segments/destinations (i.e. newly unused pages/blocks) are going to need to be selected in order to store additional data)
In regards to claims 4, 11, and 17 Tanpairoj further teaches and/or makes obvious
wherein collecting the one or more operating statistics comprises collecting at least one of an amount of free space in the primary storage band of the memory device, an amount of valid data in the primary storage band of the memory device, or an amount of data written by a host system to the cache of the memory device. (¶66 teaches that conditions (i.e. operating statistics) for initiating the migration process can be the amount of free space of the MLC (primary storage band), the amount of free space in the SLC cache (i.e. an amount of data written by a host system to the cache), and the fragmentation levels (i.e. an indication of the levels of valid vs. invalid data) of the SLC cache and MLC (primary storage band).
In regards to claims 5, 12, and 18 Tanpairoj further teaches and/or makes obvious
wherein determining the target rate for migrating data from the cache to the primary storage band of the memory device comprises balancing the amount of free space in the primary storage band of the memory device with the amount of data written by the host system to the cache of the memory device. (¶60 teaches that “the SLC cache provides a balance between the speed of the SLC memory cells with the storage capacity (free space) of the MLC (primary storage band)”. ¶61-62 teaches that in order to continue to use the increased performance of the SLC for new requests (i.e. the amount of data written to the cache by the host) that migration of the data will need to be properly managed and that SLC migration profiles are implemented to define a set of rules that evaluate current operational parameters to determine when and how much data to migrate from the SLC cache to the MLC.)
In regards to claims 7, 14, and 20 Tanpairoj further teaches and/or makes obvious
wherein the processing device is to perform operations further comprising: determining, based on the target rate for migrating data from the cache to the primary storage band of the memory device, a target rate at which data is written from a host system to the cache of the memory device. (¶71-73 teaches that the command queue depth of the host (i.e. rate at which data is written to the host) can be used as one of the factors in determining when to start, stop and/or adjust the rate of migration of data from the SLC to MLC. As such for each of the target rates for migrating data, there is a “target rate at which data is written from the host” that must be maintained for the selected migration data rate. For example, it is suggested that migration only happen when the queue depth is zero (i.e. the target rate at which data is being written by the host is 0), such that migration only happens while the system is in an idle state and that migration may be terminated if the queue depth is not 0 (i.e. outside the target rate of which data is written from the host), such that the system can focus its resources on processing the host data in the most efficient manner possible.
Claim(s) 6, 13, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj (US 2109/01369899) in view of in view of Hida (US 2012/0159051, as listed on the IDS dated 3/20/2026) and He (US 2020/0401513).
In regards to claims 6, 13, and 19 Tanpairoj teaches
In ¶71-73 that the command queue depth of the host may be used as a trigger for instantiating operations that are to be performed during background/idle periods. However Tanpairoj or Hida may not specifically teach
wherein configuring one or more data rate control parameters of the system comprises adjusting a rate at which data is folded within the primary storage band of the memory device.
It should be noted that the applicant’s specification refers to “folding” as performing garbage collection (i.e. collecting valid pages from blocks with a mix of valid/invalid pages and rewriting the valid pages to a new block and erasing the block with invalid pages)
He in ¶98 and fig. 8 step 820 teaches that GC operations may be initiated and/or adjusted based on host or physical write metrics and performed in the background when the host is idle, and that ¶103-104 and Fig. 9 step 942 and 952 teaches that the rate at which GC operations (i.e. speed, frequency, time duration, number of erase blocks targeted) can be adjusted based off current operational conditions (in this case whether the actual write amount is either above or below an expected targeted amount).
As such, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to modify the system of Tanpairoj and Hida to incorporate the teachings of He such that control parameters could be adjusted in order to control the rate, speed, frequency in which garbage collection operations (i.e. data is folded in the MLC, primary storage band) based upon the current operation conditions of the memory device and a trigger event/condition occurring. The motivation for such a modification is that this allows memory blocks to freed up in MLC, and for this process to occur during the idle periods of the storage device in order to prevent interfering with higher priority I/O requests from a host system.
EXAMINER’S NOTE
Examiner has cited particular paragraphs, figures, and/or columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON W BLUST/Primary Examiner, Art Unit 2132
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