DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
2. Claims 1, 3, 10 & 17-18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 & 9 of copending Application No.18/790,372 (same assignee) in view of Scheuerlein et al (US 8,284,589). Although the claims at issue are not identical, they are not patentably distinct from each other because the following comparisons:
The two independent claims 1 & 17 (this application ‘225) obviously read on most the limitations from claim 1 (copending application ‘372 above); for example, a memory device with a bleeder device coupled to local digit/bit line and multiple voltage sources. Particularly, it would have been obvious to a skilled person in this art as follows:
The “bleeder supply circuit” recited in claim 1 (application) obviously read on the “bleeder device” recited in claim 1 (patent);
The “multiple voltage sources” recited in claim 1 (application) obviously read on the “plurality of capacitors” recited in claim 1 (patent);
The “switch coupled to select the multiple voltage sources” recited in claim 1 (application) obviously read on the “access devices coupled to select plurality of capacitors” recited in claim 1 (patent);
The “local digit line” recited in claim 1 (application) obviously read on the “local sense line” recited in claim 1 (patent) because any sense amplifier must directly couple to the bit line for sensing its line voltage;
The “global digit line” recited in claim 1 (application) obviously read on the “global sense line” recited in claim 1 (patent) because any global sense amplifier must also couple to a global I/O line too as well-known in this art.
Additionally, regarding the limitation of “three-dimensional memory device with plural tiers or arrays”, or 3D cell structure, from claim 1 (application), the patent claim 1 does not recite this feature; however, other similar prior arts which disclose a similar “bleeder device” for a memory array further suggested that this usage applied to a 3D memory structure as well. For example, the prior teachings of Scheuerlein et al (US 8,284,589), see Fig. 10A-10B, has shown usage of a bleeder element (300b) connected to plurality of voltage supply sources (5v, 6V, & GND) for bleeding the current applied to a local digit line, and Fig. 9A-9B also shows a 3D memory structure having many cell layers as the claimed ”cell tiers” as well. Thus, it would have been obvious to a skilled person in this art, at the time of this invention, that the “bleeder device” as claimed by the co-pending application ‘372 also could have been similar used in any other 3D memory device without hindrance (per Scheuerlein suggestion) as long as the purpose of “bleeding the current feeding into the local bit line” is similarly suggested by both teachings. Thus, they are drawn to a same inventive concept.
Claims 3 & 18 (application), the term “multiplexer” obviously read on the term “multiplexor” of claim 1 (application ‘372).
Claim 10 (application) recites same language taken from claim 9 (application ‘372).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1, 5, 10 & 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scheuerlein (US 8,284,589).
Regarding the independent claims 1 & 17, Scheuerlein (see Figs. 9A-9B) shows a 3D memory structure comprising a cell array 900 forming by a plurality of vertical tiers (or layers of cells), wherein each memory cell coupled to a logic digit/bit line and at least a global digit/bit line (located at the bottom layer) is also coupled to its respective local digit lines as claimed. Furthermore, Fig. 10A-10B shows usage of at least switch/access (or transistors (163’ & 314’) coupled to a plurality of supply voltage sources (5V, 5V, & ground) to select one of these voltage sources to couple to each local digit line, and at least a blleder device (diode 300b) coupled to the transistor switch and to the local digit line so as to set the local digit line to a voltage bases on the selection of the switch. See illustrations below:
[AltContent: arrow][AltContent: arrow][AltContent: textbox (- Plural voltage sources = 304 + 120 + 305 (5v, 5v & ground GND)
- Access/switch to select voltage sources = two transistors 163’ & 314’
- Bleeder supply circuit = Diode & resistor 300b for reducing/l or limiting the current so as to set the local digit/bit line to 0.8V, based on access/switch enabled.)]
[AltContent: arrow]
[AltContent: arrow][AltContent: textbox (Local digit line coupled to a memory cell
140)]
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Claim 5, when any a cell is selected for access (in a read or write operation), then the controller will also control the switch to activate the bleeder to couple voltage to the selected local digit line as well.
Claim 10, Fig. 10A shows the bleeder located near the top edge of the array.
Allowable Subject Matter
4. The claim group 11-16 contains allowable subject matter over prior arts of record for reciting a novel method of operating a 3DF memory device comprising the following steps:
- charging, using a switch arranged to select one of multiple sources, a local digit line to a local digit line reference voltage from an idle digit line voltage through a bleeder supply circuit coupled to the local digit line before a digit line multiplexer turns on, the local digit line coupled to the digit line multiplexer and coupled to a set of memory cells in different tiers of an array of memory cells of the three- dimensional memory device; and
- switching the bleeder supply circuit off; and
- sharing, after the bleeder supply circuit turns off, the local digit line reference voltage from the local digit line to a global digit line coupled to the digit line multiplexer.
Additionally, the following dependent claims 2, 4, 6-9 & 19-20 are objected as being dependent upon their parent (rejected) claims, but they also add further novel libations to the recited structure of both claims 1 or 18, which are not clearly suggested by the prior arts at this time:
Claims 2 add usage of an “idle digit line voltage source” and a “local digit line reference voltage source”;
Claim 4 adds usage of another bleeder circuit coupled to another switch access of another local line plus a global line;
Claims 6-9 add usage of another cell array with its local digit line acting as the local reference source couple to sense amplifier for sensing purpose.
Claims 19-20 add usage of another cell array with its global digit line acting as the global reference source couple to sense amplifier for sensing purpose.
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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