DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, 11, 16-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goo et al. (US 2021/0158848 cited by Applicant in the IDS filed on 11/20/2024).
Regarding claims 1, 11 and 18, Goo discloses an input/output (I/O) interface of a memory device, configured to:
receive a first address of first data to be read (paragraph [0030], lines 5-7, address to read data D0 to D4 in Fig. 3);
receive warmup information that indicates a warmup period before reading the first data (paragraph [0006], lines 8-11 and Fig. 3, Warm-up Cycles: 2); and
determine, based on the first address (Fig. 3, address of D0-D4) and the warmup information, a second address of second data (D6 and D7) to be read during the warmup period before reading the first data.
Regarding claim 11, Goo discloses a memory cell array 110 in Fig. 4 and peripheral circuits include an address decoder, a voltage generator, a read/write circuit 123 and a data input/output circuit 123.
Regarding claim 18, Guo discloses a memory controller and a memory device in Fig. 1.
Regarding claim 10, Goo (Fig, 3) shows the I/O interface of claim 1, configured to:
output the second data (D6 and D7) during the warmup period; and
output the first data (D0-D4) after the warmup period.
Regarding claim 16, Goo discloses the memory device of claim 11, wherein the peripheral circuits are configured to:
read the second data during the warmup period; and
read the first data after the warmup period (see the rejection of claim 10).
Regarding claim 17, Goo discloses the memory device of claim 1, wherein the memory device comprises a NAND memory device (paragraph [0031], line 2)
Regarding claim 20, Goo discloses the memory system of claim 18, wherein the peripheral circuit is configured to:
read the second data during the warmup period; and
read the first data array after the warmup period (see the rejection of claim 10).
Allowable Subject Matter
Claims 2-9, 12-15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the I/O interface comprises an address shifter and a first frequency divider coupled to the address shifter, wherein the address shifter is configured to: determine the first address less a quantity of warmup cycles as the second address; and send the second address to the first frequency divider.” in combination with the other limitations thereof as is recited in the claim. Claims 3-7 depend on claim 2.
Regarding claim 8, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “in response to receiving a read command to read the first data: reset a data path of the I/O interface during a first pulse; read data based on a fourth least significant bit of the second address during a second pulse; read data based on a third least significant bit of the second address during a third pulse; and read data based on a second least significant bit of the second address during a fourth pulse.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “in response to receiving, after a read pause, a read resume command to read the first data: reset a data path of the I/O interface during a first pulse; read data based on a fourth least significant bit of the second address during a second pulse; read data based on a third least significant bit of the second address during a third pulse; and read data based on a second least significant bit of the second address during a fourth pulse.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the I/O interface comprises an address shifter and a first frequency divider coupled to the address shifter, wherein the address shifter is configured to: determine the first address less a quantity of warmup cycles as the second address; and send the second address to the first frequency divider.” in combination with the other limitations thereof as is recited in the claim. Claims 13-15 depend on claim 12.
Regarding claim 19, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein determining the second address comprises: determining the first address less a quantity of warmup cycles as the second address.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Slobodnik (US 2003/0167426) discloses a method and an apparatus for memory self testing.
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/HUAN HOANG/ Primary Examiner, Art Unit 2827