Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 08/01/24. Claims 1-20 are pending in this application.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. §102(a)(1) and (a)(2) as being unpatentable over Yi (US 2020/0083319 A1).
Regarding claim 1, Li, at least at fig 12, discloses a semiconductor device, comprising:
a first group including a plurality of first neighboring bottom electrodes over the substrate (left 202/160/170/200);
a second group including a plurality of second neighboring bottom electrode over the substrate (right 202/160/170/200); a first supporter disposed between the first neighboring bottom electrodes to support the first neighboring bottom electrodes (see left 160);
a second supporter disposed between the second neighboring bottom electrodes to support the second neighboring bottom electrodes(see left 160), wherein the first support and the second support are isolated from each other(see left 160 are separated from right 160); and
a supporter reinforcement layer disposed between the first or second neighboring bottom electrodes and the first or second supporter(see fig 12, diagonal 202).
Regarding claim 2, Li discloses the semiconductor device of claim 1, wherein the supporter reinforcement layer fully covers a contact surface between the first or second supporter and the first or second neighboring bottom electrode (see diagonal surface is fully covered by 202, fig 14).
Regarding claim 3, Li discloses the semiconductor device of claim 1, wherein the supporter reinforcement layer has a closed loop shape that surrounds the outer wall of the first or second neighboring bottom electrode (see fig 2, where diagonal slope is conical).
Regarding claim 4, Li discloses the semiconductor device of claim 1, wherein the supporter reinforcement layer has a broken loop shape that partially surrounds the outer wall of the first or second neighboring bottom electrode (see fig 12, where 202 is not continuous across 200).
Regarding claim 5, Li discloses the semiconductor device of claim 1, wherein a side profile of the first or second supporter reinforcement layer has one shape among a curved shape, a vertical shape, and a tapered shape (see fig 12, disclosing 202 has a tapered shape).
Regarding claim 6, Li discloses the semiconductor device of claim 1, wherein the supporter reinforcement layer includes a material that selectively grows from the first or second supporter (see para [0072], disclosing formation of 202).
Regarding claim 7, Li discloses the semiconductor device of claim 1, wherein the first or second supporter layer and the supporter reinforcement layer include a nitrogen-containing material(see para [0072], disclosing formation of 202, AlN).
Regarding claim 8, Li discloses the semiconductor device of claim 1, wherein the first or second supporter layer and the supporter reinforcement layer include silicon nitride, silicon carbon nitride, silicon boron nitride, or a combination thereof (see para [0056] disclosing SiCN).
Regarding claim 9, Li discloses the semiconductor device of claim 1, wherein the first or second neighboring bottom electrode has a shape among a pillar shape, a cylinder shape, and a cylinder shape (see fig 2, where 200 is a cylinder).
Regarding claim 10, Li discloses the semiconductor device of claim 1, wherein the supporter reinforcement layer extends to cover the upper surface of the first or second supporter from the interface between the first or second supporter and the first or second neighboring bottom electrode (see fig 12, where 202 covers an upper diagonal surface at 200).
Regarding claim 11, Li discloses the semiconductor device of claim 1, further comprising: an additional supporter reinforcement layer that selectively grows from at least one between the first or second supporter and the supporter reinforcement layer(see para [0072], disclosing formation of 202).
Regarding claim 12, Li discloses the semiconductor device of claim 1, wherein the first or second supporter includes a multi-level supporter (see fig 12, disclosing a multi-level structure), and the supporter reinforcement layer includes a multi-level supporter reinforcement layer which is positioned between the multi-level supporter and each of the first or second neighboring bottom electrodes (see at least three 200 sections in fig 12).
Regarding claim 13, Li discloses the semiconductor device of claim 12, wherein an uppermost-level supporter reinforcement layer of the multi-level supporter reinforcement layer has a broken loop shape that partially surrounds the outer wall of the first or second neighboring bottom electrode (see 202 is discontinuous, fig 12, fig 2).
Regarding claim 14, Li discloses the semiconductor device of claim 12, wherein supporter reinforcement layers positioned at a lower level than the uppermost-level supporter reinforcement layer in the multi-level supporter reinforcement layer has a closed loop shape that surrounds the outer wall of the first or second neighboring bottom electrode (see figs 2 and 12, disclosing a lower conical element of 202 that is discontinuous).
Regarding claim 15, Li discloses the semiconductor device of claim 12, wherein the uppermost-level supporter reinforcement layer 202 of the multi-level supporter reinforcement layer 160 extends to cover the upper surface of the first or second supporter from an interface between an uppermost-level supporter of the multi-level supporter and the first or second neighboring bottom electrode (see sloping portion of 202).
Regarding claim 16, Li discloses the semiconductor device of claim 12, wherein the uppermost-level supporter reinforcement layer of the multi-level supporter reinforcement layer and the uppermost-level supporter of the multi-level supporter are disposed at higher level than a top surface of the first or second neighboring bottom electrode.
Regarding claim 17, Li discloses the semiconductor device of claim 12, wherein the uppermost-level supporter reinforcement layer of the multi-level supporter reinforcement layer and the uppermost-level supporter of the multi-level supporter are positioned at a lower level than a top surface of the first or second neighboring bottom electrode (see 202 covering a top of 200, figs 2 and 12).
Regarding claim 18, Li discloses the semiconductor device of claim 1, further comprising: a dielectric layer on the bottom electrode, the first or second supporter, and the supporter reinforcement layer; and a top electrode on the dielectric layer (see 202 comprising a dielectric layer covering/having diagonal portions of 202).
Regarding claim 19, Li discloses the semiconductor device of claim 1, further comprising: a buried word line formed in the substrate; and a bit line formed over the substrate ( see 140).
Regarding claim 20, Li discloses the semiconductor device of claim 1, wherein the first support and the second support have a same planar shape over the substrate, the planar shape determined based on how many the first or second neighboring bottom electrodes are included in the first or second group individually (see 160, 170, 180 having planar shapes).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/ Primary Examiner, Art Unit 2893
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